Commit Graph

8173 Commits

Author SHA1 Message Date
James E. Stine
6894ee4588 Separate gm2.sv to be separate module 2024-03-05 09:10:41 -06:00
James E. Stine
5aab40a35f Missed some style module declarations 2024-03-05 09:06:48 -06:00
James E. Stine
5e247b9bf3 fix some spacing in aes_common 2024-03-05 09:02:22 -06:00
James E. Stine
7bbc6413fb fix spacing in sha_instructions for style 2024-03-05 08:59:45 -06:00
James E. Stine
0d7ea36883 fix module name to lc in aes_instructions 2024-03-05 08:56:24 -06:00
James E. Stine
e6ffde61bd fix module name to lc 2024-03-05 08:54:50 -06:00
David Harris
1a0097f6e7 Further fdivsqrt simplification after starting Sqrt at iteration 0 2024-03-04 16:40:49 -08:00
David Harris
9c04df8f69 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-03-04 16:04:24 -08:00
David Harris
2e31bf021c
Merge pull request #646 from kevindkim723/sqrtbugfix_USLC
Square root R=4 K=2 bug fix
2024-03-04 16:04:14 -08:00
Rose Thompson
457d3481e7 How did this error get past for so long. 2024-03-04 17:58:41 -06:00
Rose Thompson
0222e8f42a Don't want to clear the lru bits on invalidation (clearvalid). 2024-03-04 17:52:41 -06:00
Kevin Kim
10ab07975f uslc comments 2024-03-04 14:31:21 -08:00
Kevin Kim
9b87a00698 sqrt mux lint fixes 2024-03-04 14:31:07 -08:00
Kevin Kim
587fdbdf8e removed j1,j0 from iteration and put inside divider stage 2024-03-04 14:30:05 -08:00
KelvinTr
c163069484 Optimized mixcolumn 2024-03-04 15:23:11 -06:00
Kevin Kim
7dec9cdf21 optimization in uslc 2024-03-04 10:46:16 -08:00
Kevin Kim
9c95cba865 remove sqrt cycle muxing 2024-03-03 18:51:10 -08:00
Kevin Kim
0ff59ff157 remove redundant mux 2024-03-03 13:00:20 -08:00
Kevin Kim
2547e4c6d1 divider still works with NF+2 2024-03-03 11:17:51 -08:00
Kevin Kim
c32173f163 changed U/C initialization to account for integer bit generation on divider stage for sqrt. Quick and dirty j1 logic fix 2024-03-03 10:30:18 -08:00
Kevin Kim
6c24afaf98 changed cycle count to account for integer bit generation for sqrt 2024-03-03 10:29:32 -08:00
Kevin Kim
c45d67f8ba fdivsqrt changes 2024-03-02 20:29:03 -08:00
Kevin Kim
77ccc7b319 removed square root pre-process muxes 2024-03-02 15:55:34 -08:00
Rose Thompson
a22de45631 Removed unused storedelay from align. 2024-03-02 16:20:31 -06:00
Rose Thompson
8136b45ca7 Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
This reverts commit cba3209e7f.
2024-03-02 11:55:43 -06:00
Rose Thompson
cba3209e7f Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned. 2024-03-02 11:38:33 -06:00
Rose Thompson
4c3d927474 Renamed CacheHit to Hit. 2024-03-01 11:00:24 -06:00
Rose Thompson
60f96112db Moved the zero stage boot loader to the fpga directory. 2024-03-01 10:23:55 -06:00
Rose Thompson
e72880fd89 Changed cachefsm state STATE_HIT to STATE_ACCESS. 2024-03-01 09:59:54 -06:00
Rose Thompson
85691f0e8b Simplified and clarified names in cacheLRU. 2024-02-29 17:18:01 -06:00
KelvinTr
c110d0bb03 Optimized Zbkx 2024-02-29 14:51:02 -06:00
KelvinTr
9f53c54f57 Optimized Zbkx 2024-02-29 14:50:15 -06:00
KelvinTr
e40ae126d3 Combined ZBC and ZBKC into one unit 2024-02-29 14:17:33 -06:00
KelvinTr
88d93b31b5 Combined byteop and revop logic 2024-02-29 12:51:42 -06:00
Rose Thompson
90ad5e7dab Updated the cache for book clarity. 2024-02-28 17:07:32 -06:00
KelvinTr
01c45ab9d7 Fixed K extension changes 2024-02-28 17:05:08 -06:00
David Harris
90e89ced1d Fixes for synthesis. HPTW change will break x detection 2024-02-26 04:20:08 -08:00
James E. Stine
0d4d996655 add spike riscof items for K extension test 2024-02-24 22:43:33 -06:00
James E. Stine
eb1780a66d control for bitmanip 2024-02-24 22:38:21 -06:00
James E. Stine
ce975a6336 Add ieu main module for k extension 2024-02-24 22:37:04 -06:00
James E. Stine
71cefdbbb2 main cvw module 2024-02-24 22:35:56 -06:00
James E. Stine
cd2a9b8712 Add mux7 for K ext 2024-02-24 22:26:21 -06:00
James E. Stine
50cbe54d7b Add datapath.sv 2024-02-24 22:22:19 -06:00
James E. Stine
e06bafe972 Add alu + controller 2024-02-24 22:21:39 -06:00
Rose Thompson
252ca5b925 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-02-23 14:11:18 -06:00
Rose Thompson
ab750e150f Fixed lint errors for alignment. 2024-02-23 14:00:19 -06:00
Rose Thompson
a2d5618d88 Added sdc to pma allow shift. 2024-02-23 13:46:04 -06:00
Rose Thompson
e84b7cc147 Cleanup. 2024-02-23 13:00:21 -06:00
Rose Thompson
ae36f1e5a5 Merge branch 'main' of github.com:ross144/cvw 2024-02-23 09:43:03 -06:00
Rose Thompson
caac48b7f2 Removed duplicate endianswap. 2024-02-23 09:42:39 -06:00