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281 Commits

Author SHA1 Message Date
David Harris
225102047a Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
David Harris
bad180fc15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2 Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b Fixed previous commit 2021-02-25 11:24:44 -06:00
Teo Ene
5fee65231e Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
Teo Ene
b9701293a0 Changed TIMBASE in coremark config file 2021-02-25 11:03:41 -06:00
Teo Ene
8491deb1a9 Changed .do file back to run all 2021-02-25 09:58:54 -06:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
cfd45a46c3 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
kaveh pezeshki
251aa982eb condensed always blocks to avoid race conditions 2021-02-24 11:35:28 -08:00
Noah Boorstin
ddaf67c043 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
kaveh pezeshki
06f73fe5fe added comments for RAM and bootram, removed trailing whitepace 2021-02-23 21:28:33 -08:00
Noah Boorstin
b7f4e72eec busybear: add bootram section in the same manner as ram 2021-02-24 02:02:28 +00:00
Noah Boorstin
914a36e3e8 busybear: add support for subwords in ram 
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
 2021-02-24 01:51:18 +00:00
Noah Boorstin
7b7e87bd0b busybear: start adding ram 2021-02-23 22:01:23 +00:00
Katherine Parry
07641203ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-23 20:21:53 +00:00
Katherine Parry
906ec30339 inital FMA push 2021-02-23 20:19:12 +00:00
Noah Boorstin
5394d38e4a busybear: remove unused signals 2021-02-23 19:38:19 +00:00
Noah Boorstin
c42c485377 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
7737b0f709 Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
c856003f73 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
06e975ac2f minor change to wave file. 2021-02-19 09:08:13 -06:00
Ross Thompson
7d6093b302 Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Thomas Fleming
ca51e7ca1c Create simple TLB 
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
 2021-02-18 18:06:09 -05:00
David Harris
87ad559a90 Updated creation date of mul 2021-02-18 08:13:08 -05:00
Ross Thompson
8cbc9f7e51 Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. 
Once combined with some simulation verilog this will display the current function in modelsim.
 2021-02-17 22:20:28 -06:00
Ross Thompson
bbe0db3ebe Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
fe7299c155 Resotred part of multiplier for lab 2 2021-02-17 16:14:04 -05:00
David Harris
492ec0ee78 Removed multiplier for lab 2 2021-02-17 16:06:16 -05:00
David Harris
e8d3c7d9e7 Multiplier tweaks 2021-02-17 16:00:27 -05:00
David Harris
e64e8afb7f Started to integrate OSU divider 2021-02-17 15:38:44 -05:00
David Harris
a7dd20b388 Multiply instructions working 2021-02-17 15:29:20 -05:00
Noah Boorstin
43f9abdbed busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
adc5d5bc1a Added MUL 2021-02-15 22:27:35 -05:00
Ross Thompson
ca546beaf8 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. 
This is not yet tested but the system verilog does compile.
 2021-02-15 14:51:39 -06:00
David Harris
3900abeb86 WALLY ALU tests 2021-02-15 10:16:31 -05:00
David Harris
cc42655789 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
Domenico Ottolia
3ee975dd5a Add privileged test cases 2021-02-14 17:01:46 -05:00
Ross Thompson
935e9e59e9 added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior. 2021-02-14 15:13:55 -06:00
Ross Thompson
8486f426b7 The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables. 2021-02-14 11:06:31 -06:00
Shreya Sanghai
4e887f83a3 added branch tests 2021-02-12 22:40:08 -05:00
Noah Boorstin
84d856d1e5 busybear: allow testbench to ignore lack of MMU for now 
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing

If it is, we're at 1M instructions!
 2021-02-12 20:08:56 +00:00
Noah Boorstin
dd3a5b74a1 busybear: slightly neater error handling 2021-02-12 17:21:56 +00:00
bbracker
deb7780897 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
Noah Boorstin
79fb83409f bump into virtual/physcial memory? 2021-02-11 23:06:12 -05:00
Noah Boorstin
e89af96bc0 busybear: more updates 
now gets to instruction 839037 before failing
also updates to match new gdb output format

umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
 2021-02-11 22:42:58 -05:00
Tejus Rao
fb6a4bbbf0 added test cases for ADDW, SUBW, SLLW, SRLW, SRAW 2021-02-11 13:38:38 -05:00
Teo Ene
5f84ed407c Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts 2021-02-10 20:48:39 -06:00
ethan-falicov
7925fe3131 Fixed merge conflict stuff 2021-02-10 10:03:30 -05:00
ethan-falicov
06517631cc More merge conflicts yay 2021-02-10 09:54:30 -05:00
ethan-falicov
863796b3c1 Merge conflict fixing 2021-02-10 09:45:47 -05:00
ethan-falicov
67662b888e Adding I Type test cases from Lab 1 2021-02-10 09:39:43 -05:00
David Harris
b121b90b28 Debugging bus interface. 2021-02-10 01:43:54 -05:00
David Harris
842c374de9 Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
74bc4c0444 Fixed lw by delaying read value by one cycle 2021-02-07 23:28:21 -05:00
David Harris
33110ed636 Data memory bus integration 2021-02-07 23:21:55 -05:00
Jarred Allen
e334475ab5 Fix compile error in imperas testbench 2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
805817cda4 merge conflict? 2021-02-07 02:34:49 -05:00
Noah Boorstin
01b1b1705d Busybear: next week of updates 
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
 - parsed first 1M instructions, and now parse from split GDB runs
 - now at about 230k instructions, can't progress further for now since atomic instructions
   aren't implemented yet
 2021-02-07 03:14:48 +00:00
Jarred Allen
29b7a0cd25 Actually run the WALLY-LOAD tests 2021-02-06 14:56:40 -05:00
Jarred Allen
a3f2f4c7bc Add test vector set for load instructions 2021-02-06 13:05:59 -05:00
bbracker
15c0b4af22 JAL testing 2021-02-05 08:08:42 -05:00
Noah Boorstin
c03f69fb80 Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
Thomas Fleming
8d7a515ae7 Complete STORE tests 2021-02-04 15:38:22 -05:00
Noah Boorstin
fc734eb14e busybear: add more CSRs 2021-02-04 20:13:36 +00:00
Noah Boorstin
77a88d8019 busybear: check initial values also 2021-02-04 19:22:09 +00:00
Brett Mathis
11e2666bb2 Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
Jarred Allen
088fbbcbf0 Change busybear test to use work-busybear library 2021-02-03 11:12:47 -05:00
Jarred Allen
f700efc2b3 Start on a test set for loads 2021-02-03 00:37:43 -05:00
David Harris
2a80bcf543 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 19:44:43 -05:00
David Harris
756352f129 Minor tweaks 2021-02-02 19:44:37 -05:00
Jarred Allen
e5bd749e2a Refactor regression test 2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9 Add busybear testbench to nightly regression checking 
If you don't like how I did this please feel free to undo it
 2021-02-02 22:05:35 +00:00
Noah Boorstin
b5f474d9f5 same thing but do that right this time 2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55 change undefined syntax in extend.sv 
don't need verilator execption anymore
 2021-02-02 21:39:20 +00:00
David Harris
429f48e766 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
9f9c3bcece Changed DTIM latency to 2 cycles 2021-02-02 14:22:12 -05:00
David Harris
616830a3f0 Cleaned up hazard interface 2021-02-02 13:53:13 -05:00
David Harris
587a343dac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 13:42:35 -05:00
David Harris
229bde5953 Moved LoadStall generation to IEU 2021-02-02 13:42:23 -05:00
David Harris
bb83fda1d8 Moved writeback pipeline registers from datapth into DMEM and CSR 2021-02-02 13:02:31 -05:00
Jarred Allen
da43b2be53 Fix intermittent errors caused by weird library stuff 2021-02-02 11:20:09 -05:00
Noah Boorstin
f1768ee50b Busybear: start checking CSRs 
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)

and 3 of the CSRs referenced are skipped because of weird locations for them

oh and this doesn't check their initial state, just their changing. This could be a problem
 2021-02-02 06:06:03 +00:00
David Harris
92bf1674b4 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
Jarred Allen
f143518b23 Fix issues in parallel regression testing 2021-02-01 23:29:03 -05:00
Noah Boorstin
38265c03b7 busybear: start adding CSR checking 
@kaveh is there a less verbose way to do this?
 2021-02-01 22:08:51 -05:00
Brett Mathis
bcb722272e OSU FPU IP initial commit 2021-02-01 19:33:43 -06:00
Noah Boorstin
d592db79c9 busybear: change register file checking to only store register changed 
this should make parsedRegs.txt much smaller
 2021-02-02 01:27:43 +00:00
Noah Boorstin
71f5bb0ce8 Add PCW checking 
for now, doesn't check InstrW because it fails on compressed instructions
 2021-02-01 23:57:33 +00:00
David Harris
1a3963bed0 Renamed DCU to DMEM 2021-02-01 18:52:22 -05:00
Jarred Allen
5cf3d188c6 Parallelize regression-wally.p 2021-02-01 15:40:27 -05:00
Noah Boorstin
1b9ec8b339 busybear: print warning when NOPing out instructions 2021-02-01 19:44:56 +00:00
Noah Boorstin
a82f8977c6 busybear: NOP out floating point instructions for now 
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
 2021-01-30 19:52:47 +00:00
Noah Boorstin
cca60ed06d update busybear testbench to conform to new structure 
aaaaaaaaaaaaaaaaaahhhh so many changes

also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
 2021-01-30 19:19:00 +00:00
David Harris
07af481b67 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
29313a108b Working on reading instruction from TIM 2021-01-30 01:57:51 -05:00
David Harris
5429424871 Adding stalls for memory delays 2021-01-30 01:43:49 -05:00
David Harris
26c560fba3 Added HCLK and HRESETn 2021-01-30 00:56:12 -05:00
David Harris
9511dcac84 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
9297376873 Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team 2021-01-29 18:06:36 -05:00
David Harris
6c76962847 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 17:29:01 -05:00
David Harris
9530039e3d Implemented adrdec for uncore 2021-01-29 17:28:53 -05:00
Teo Ene
5e5e03c717 - Removed latch on CSRCReadValM in csrc.sv 
- Changed top level to wallypipelinedhart
 2021-01-29 15:56:51 -06:00
David Harris
6d5b01357d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 15:38:01 -05:00
David Harris
d104e5a4be Moving data memory to uncore 2021-01-29 15:37:51 -05:00
Teo Ene
f0bbd71874 Added AHBW to rv32ic config file as well 2021-01-29 12:29:08 -06:00
Noah Boorstin
7183910c84 update busybear testbench to conform to new structure 2021-01-29 17:46:50 +00:00
David Harris
4687d6998a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 01:07:22 -05:00
David Harris
e4e95bf941 Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
Noah Boorstin
0fa7cffb11 busybear: lie about MISA to match OVP's MISA 2021-01-29 00:58:56 -05:00
Noah Boorstin
84e4193db6 busybear testbench: test on first 100k instrs 
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
 2021-01-29 00:14:23 -05:00
David Harris
aedadb7703 Renamed modules in privileged unit 2021-01-28 23:21:12 -05:00
David Harris
70554b94c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 21:40:57 -05:00
David Harris
004cc525e2 Hint to optimize ifu 2021-01-28 21:40:48 -05:00
Noah Boorstin
c4964352f0 busybear: simulate first 10k instructions 
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
 2021-01-28 19:44:58 -05:00
Noah Boorstin
96ceac0e80 busybear: fix misaligned writing checking 2021-01-28 19:35:09 -05:00
Noah Boorstin
df1d174aea busybear: add more test instructions 
currently testing first 1k instrs
 2021-01-28 16:41:37 -05:00
Noah Boorstin
9c0580f2e1 oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench 2021-01-28 16:35:12 -05:00
Noah Boorstin
cbab07967a more of the same fixes 2021-01-28 16:26:15 -05:00
Noah Boorstin
03cea6e29b more misaligned read fixing 
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
 2021-01-28 16:14:35 -05:00
David Harris
3e786729ac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 15:44:14 -05:00
David Harris
1ad69b52d5 Fixed floating signals in clint and ieu 2021-01-28 15:44:05 -05:00
Noah Boorstin
e65166bec5 busybear testbench: understand bytemask for writes 2021-01-28 15:42:47 -05:00
David Harris
8eebf01dca Fixed c.jr instruction improperly writing ra 2021-01-28 15:18:23 -05:00
Noah Boorstin
9a45b49536 busybear: ret is only 1 word 2021-01-28 14:47:40 -05:00
Noah Boorstin
5a5237b908 add speculative exception for compressed instructions 2021-01-28 14:40:35 -05:00
Noah Boorstin
632fecf43a testbench now understands lw not aligned to 8 bytes 
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
 2021-01-28 13:33:22 -05:00
Noah Boorstin
e19af0a52a busybear testbench: check for read data address also 
and check for more end of files better
 2021-01-28 13:16:38 -05:00
Noah Boorstin
7fd73d12e9 update busybear testbench to conform to new structure 2021-01-28 01:21:47 -05:00
Noah Boorstin
be3d024527 Busybear test now processes first 100 instrs correctly! 
- changed test parser to recognize lw in addition to lw

also, added temporary questa files (wlft*) to .gitignore
 2021-01-28 01:19:27 -05:00
Noah Boorstin
ed85fda42a fix memory write address decoding for busybear tests 2021-01-28 01:19:26 -05:00
David Harris
52d6a01cea Created DCU and moved memdp into DCU 2021-01-28 01:03:12 -05:00
David Harris
01e37210ea Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 00:22:11 -05:00
David Harris
af25784b61 Provided PC + 2 or 4 (PCLink) for JAL 2021-01-28 00:22:05 -05:00
Noah Boorstin
840528a05f update busybear testbench to conform to new structure 2021-01-27 23:42:19 -05:00
David Harris
9d821aab0f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 22:49:55 -05:00
David Harris
37a58cea17 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
Noah Boorstin
74e57a8472 update busybear testbench to conform to new structure 2021-01-27 12:54:09 -05:00
David Harris
db5f45c240 Moved privileged unit from datapath to hart 2021-01-27 07:46:52 -05:00
David Harris
092edf953e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 06:40:39 -05:00
David Harris
4318629b32 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
Noah Boorstin
91564c7ab1 show instruction assembly in waveform 2021-01-26 12:34:12 -05:00
Noah Boorstin
91dcffa26f Update busybear tests to conform to new directory structure 2021-01-25 20:37:18 -05:00
Noah Boorstin
09c92a6b5d Fixed mem write checking 
now passes around 50 instructions!
 2021-01-25 20:07:08 -05:00