Rose Thompson
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2ea0134329
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Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
This reverts commit cba3209e7f.
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2024-03-06 13:28:59 -06:00 |
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Rose Thompson
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068ffda5fb
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Revert "Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.""
This reverts commit 8136b45ca7.
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2024-03-06 13:28:47 -06:00 |
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David Harris
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e0eb91f795
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Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places
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2024-03-06 11:02:04 -08:00 |
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Thomas Kidd
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b1830b15ff
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Merge branch 'openhwgroup:main' into main
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2024-03-06 10:06:36 -06:00 |
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David Harris
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b386331cc8
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Changed '0 to 0 where possible per Chapter 4 style guidelines
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2024-03-06 05:48:17 -08:00 |
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David Harris
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dd33479056
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Switched to ?: for gating per section 4.2.4.3
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2024-03-06 04:59:58 -08:00 |
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David Harris
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86956026dc
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Further simplified subwordread muxing
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2024-03-06 04:24:31 -08:00 |
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David Harris
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9f874e835f
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Merge pull request #648 from kevindkim723/quadsubwordread_fix
lsu supports quad enabled subwordreads
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2024-03-06 04:06:50 -08:00 |
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Kevin Kim
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9d73e5bd0d
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lsu supports quad enabled subwordreads
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2024-03-05 17:07:39 -08:00 |
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KelvinTr
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00b61390d9
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Optimized Inverse Mixcolumn
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2024-03-05 14:56:24 -06:00 |
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Thomas Kidd
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baa29ea50c
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Merge branch 'openhwgroup:main' into main
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2024-03-05 14:28:05 -06:00 |
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Thomas Kidd
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22947e5b5e
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udpated readme by adding how to add crontab section
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2024-03-05 14:26:35 -06:00 |
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Rose Thompson
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c093f53c9c
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Merge branch 'main' of https://github.com/openhwgroup/cvw
Cleaned up the cacheLRU.
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2024-03-05 11:08:40 -06:00 |
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Rose Thompson
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d1a1345e4d
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Merge pull request #644 from davidharrishmc/dev
Synthesis fixes
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2024-03-05 10:39:40 -06:00 |
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Rose Thompson
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e8e0538f6c
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Changed to non-blocking in cacheLRU and removed clearing LRU bits on flush.
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2024-03-05 10:33:47 -06:00 |
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James E. Stine
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5b445946b1
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style file slight mods for sha_instructions
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2024-03-05 09:14:22 -06:00 |
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James E. Stine
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6894ee4588
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Separate gm2.sv to be separate module
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2024-03-05 09:10:41 -06:00 |
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James E. Stine
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5aab40a35f
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Missed some style module declarations
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2024-03-05 09:06:48 -06:00 |
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James E. Stine
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5e247b9bf3
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fix some spacing in aes_common
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2024-03-05 09:02:22 -06:00 |
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James E. Stine
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7bbc6413fb
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fix spacing in sha_instructions for style
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2024-03-05 08:59:45 -06:00 |
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James E. Stine
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0d7ea36883
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fix module name to lc in aes_instructions
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2024-03-05 08:56:24 -06:00 |
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James E. Stine
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e6ffde61bd
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fix module name to lc
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2024-03-05 08:54:50 -06:00 |
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David Harris
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1a0097f6e7
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Further fdivsqrt simplification after starting Sqrt at iteration 0
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2024-03-04 16:40:49 -08:00 |
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Thomas Kidd
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b2d0f71176
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Merge branch 'openhwgroup:main' into main
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2024-03-04 18:28:08 -06:00 |
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Thomas Kidd
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9ccc93ff0e
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over rides TIMEOUT on -nightly tag for regression since buildroot is not working
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2024-03-04 18:21:03 -06:00 |
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David Harris
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9c04df8f69
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2024-03-04 16:04:24 -08:00 |
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David Harris
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2e31bf021c
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Merge pull request #646 from kevindkim723/sqrtbugfix_USLC
Square root R=4 K=2 bug fix
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2024-03-04 16:04:14 -08:00 |
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Rose Thompson
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457d3481e7
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How did this error get past for so long.
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2024-03-04 17:58:41 -06:00 |
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Rose Thompson
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0222e8f42a
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Don't want to clear the lru bits on invalidation (clearvalid).
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2024-03-04 17:52:41 -06:00 |
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Kevin Kim
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10ab07975f
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uslc comments
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2024-03-04 14:31:21 -08:00 |
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Kevin Kim
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9b87a00698
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sqrt mux lint fixes
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2024-03-04 14:31:07 -08:00 |
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Kevin Kim
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587fdbdf8e
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removed j1,j0 from iteration and put inside divider stage
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2024-03-04 14:30:05 -08:00 |
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KelvinTr
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c163069484
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Optimized mixcolumn
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2024-03-04 15:23:11 -06:00 |
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Kevin Kim
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7dec9cdf21
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optimization in uslc
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2024-03-04 10:46:16 -08:00 |
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Kevin Kim
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9c95cba865
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remove sqrt cycle muxing
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2024-03-03 18:51:10 -08:00 |
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Kevin Kim
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0ff59ff157
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remove redundant mux
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2024-03-03 13:00:20 -08:00 |
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Kevin Kim
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2547e4c6d1
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divider still works with NF+2
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2024-03-03 11:17:51 -08:00 |
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Kevin Kim
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c32173f163
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changed U/C initialization to account for integer bit generation on divider stage for sqrt. Quick and dirty j1 logic fix
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2024-03-03 10:30:18 -08:00 |
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Kevin Kim
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6c24afaf98
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changed cycle count to account for integer bit generation for sqrt
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2024-03-03 10:29:32 -08:00 |
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Kevin Kim
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c45d67f8ba
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fdivsqrt changes
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2024-03-02 20:29:03 -08:00 |
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Kevin Kim
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77ccc7b319
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removed square root pre-process muxes
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2024-03-02 15:55:34 -08:00 |
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Rose Thompson
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a22de45631
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Removed unused storedelay from align.
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2024-03-02 16:20:31 -06:00 |
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Rose Thompson
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8136b45ca7
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Revert "Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned."
This reverts commit cba3209e7f.
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2024-03-02 11:55:43 -06:00 |
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Rose Thompson
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cba3209e7f
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Trying an experiment. Use the less compact subwordreaddouble in the fpga synthesize rather than subwordreadmisaligned.
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2024-03-02 11:38:33 -06:00 |
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Rose Thompson
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4c3d927474
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Renamed CacheHit to Hit.
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2024-03-01 11:00:24 -06:00 |
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Rose Thompson
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60f96112db
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Moved the zero stage boot loader to the fpga directory.
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2024-03-01 10:23:55 -06:00 |
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Rose Thompson
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e72880fd89
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Changed cachefsm state STATE_HIT to STATE_ACCESS.
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2024-03-01 09:59:54 -06:00 |
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Rose Thompson
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85691f0e8b
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Simplified and clarified names in cacheLRU.
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2024-02-29 17:18:01 -06:00 |
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KelvinTr
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c110d0bb03
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Optimized Zbkx
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2024-02-29 14:51:02 -06:00 |
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KelvinTr
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9f53c54f57
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Optimized Zbkx
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2024-02-29 14:50:15 -06:00 |
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