Xavi/cvw
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  • de6a52f6eb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-10-23 13:17:37 -0700
  • 3c0b0987d2 add option for regression to do a partial execution of buildroot bbracker 2021-10-23 13:17:30 -0700
  • 200eb453fb wrapping up lint cleanup; many unused signals removed David Harris 2021-10-23 12:15:14 -0700
  • c9e9cd4a60 more lsu/ifu lint cleanup David Harris 2021-10-23 12:10:13 -0700
  • 2cfbd888fd more lsu/ifu lint cleanup David Harris 2021-10-23 12:00:32 -0700
  • 62a23fe878 lsu/ifu lint cleanup David Harris 2021-10-23 11:41:20 -0700
  • 61fdb3d902 random lint cleanup David Harris 2021-10-23 11:24:36 -0700
  • 8d9efcbafb IEU cleanup David Harris 2021-10-23 11:13:28 -0700
  • 4bf823e063 lint cleanup David Harris 2021-10-23 11:03:28 -0700
  • d570df864f IEU lint cleanup David Harris 2021-10-23 10:51:53 -0700
  • 8e516e6391 Lint cleanup from wallypipeliendhart David Harris 2021-10-23 10:29:52 -0700
  • 33358d101e Lint cleanup: ahblite, ifu, hart David Harris 2021-10-23 10:12:33 -0700
  • d24bece3a8 Lint cleanup David Harris 2021-10-23 09:58:52 -0700
  • 2e796e3da2 lint cleanup: FPU and privileged David Harris 2021-10-23 09:41:24 -0700
  • c316bff15a subword read and csrc lint cleanup David Harris 2021-10-23 09:29:15 -0700
  • 28d8f6d5cf FMA and CSRC lint cleanup David Harris 2021-10-23 09:20:24 -0700
  • 11b0607e63 Lint cleanup David Harris 2021-10-23 09:06:21 -0700
  • ac1b1bfbb6 update scripts for handling src/*/* subdirectories David Harris 2021-10-23 08:54:29 -0700
  • 0dabb6ebd4 lint cleaning and moved files into subdirectories David Harris 2021-10-23 08:53:32 -0700
  • f483e8002a Lint cleanup David Harris 2021-10-23 08:39:21 -0700
  • cbcf6121dc hope I added logic declarations to divconv_pipe ok David Harris 2021-10-23 08:10:16 -0700
  • 3e1317b8ee Remove redundant logic value James E. Stine 2021-10-23 10:02:47 -0500
  • e2e950ac0f Cleaned up LINT erors David Harris 2021-10-23 06:28:49 -0700
  • 4c480a40f6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-23 06:15:49 -0700
  • 3249d65209 Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. David Harris 2021-10-23 06:15:26 -0700
  • 77e2b6f9a9 Merge branch 'main' into fpga Ross Thompson 2021-10-22 16:09:16 -0500
  • 2a86a6717d lowered number of paths to speed synth up and removed extra unnecessary report copying. kipmacsaigoren 2021-10-22 15:25:11 -0500
  • ef297067e9 removed reduntant definitions for FPU in MISA. kipmacsaigoren 2021-10-22 15:18:25 -0500
  • f6e8e45901 Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking James E. Stine 2021-10-22 13:41:50 -0500
  • 7c7c0f538a put the FMA priority encoders into their own module Katherine Parry 2021-10-22 10:03:12 -0700
  • 0dcca43f48 Get rid of lint warning - still need more testing though James E. Stine 2021-10-21 15:19:22 -0500
  • dd7dbaa382 Clean up some FPU and add pipelined fpdivsqrt to fpu.sv James E. Stine 2021-10-21 13:52:12 -0500
  • bafb3a983d Fix fpdivsqrt lint error on CPA for convergence James E. Stine 2021-10-20 17:46:13 -0500
  • de4ea16d32 Merge branch 'main' into fpga Ross Thompson 2021-10-20 16:24:55 -0500
  • fe24bc5a43 Added debug signals to dcache. Ross Thompson 2021-10-20 15:52:05 -0500
  • ceaf84a3ce removed .* from wallypipeliendsoc David Harris 2021-10-20 13:49:18 -0700
  • 3cdac72e96 Update README.md davidharrishmc 2021-10-20 10:49:41 -0700
  • e80fd40258 Fixed path to src and config files, added mdu timing reports kipmacsaigoren 2021-10-20 12:41:14 -0500
  • 8ea17c784a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main kipmacsaigoren 2021-10-20 12:15:53 -0500
  • ffacb7ab67 Removed historical outputs from repo kipmacsaigoren 2021-10-20 12:15:40 -0500
  • 71b48048da Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. James E. Stine 2021-10-20 12:00:41 -0500
  • 47e19d4caa moved coemark and testsBP to tests David Harris 2021-10-20 09:10:06 -0700
  • 140c80f3a8 moved imperas-riscv-tests to tests David Harris 2021-10-20 09:07:46 -0700
  • 23b3d7dbc1 Move tests into subdirectory and moved wavedrom out of project David Harris 2021-10-20 09:03:21 -0700
  • b9e3ab7e1e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-19 14:08:24 -0700
  • a88af1841f radix 2 SRT checkin David Harris 2021-10-19 14:08:16 -0700
  • af998e3e27 gitignore the addins folder because it contains external repos bbracker 2021-10-19 13:32:26 -0700
  • 41010aa418 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this James E. Stine 2021-10-19 12:09:43 -0500
  • a75abb04bd Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). James E. Stine 2021-10-19 11:58:06 -0500
  • d11136c406 Fixed bug with the external memory region selection. Updated bios program to copy just 127MB to dram. Ross Thompson 2021-10-19 11:23:23 -0500
  • 3bc985d230 Changed some flops to settable David Harris 2021-10-18 17:05:29 -0700
  • cc2b5eeed9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-18 16:54:08 -0700
  • 0516ee768b replaced flopenl with flopenr when clearing to 0 David Harris 2021-10-18 16:53:18 -0700
  • 0bb1c1c23c Update README.md davidharrishmc 2021-10-18 16:23:22 -0700
  • 398337951d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-18 15:44:31 -0700
  • 00d8035836 Fixed multiplier and pointed arch tests to new path in addins David Harris 2021-10-18 15:43:59 -0700
  • 5ce58b35a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-10-18 17:25:48 -0500
  • cd58a388e4 fixed issues with dc shell not liking modules with parameters without default values. Ross Thompson 2021-10-18 16:56:08 -0500
  • e681020d9e Update README.md davidharrishmc 2021-10-18 13:43:10 -0700
  • 197a8ca7e9 Update README.md davidharrishmc 2021-10-18 13:39:40 -0700
  • d03e42fe95 Update README.md davidharrishmc 2021-10-18 11:17:24 -0700
  • 7a36c48ac9 Update README.md davidharrishmc 2021-10-18 09:52:40 -0700
  • 37fe5e56a8 Sanitization some more on mult_cs.sv James E. Stine 2021-10-18 05:24:16 -0500
  • d0ab43e4e8 Update some on mult_cs and delete DW02_mult.v James E. Stine 2021-10-18 05:06:49 -0500
  • de7b673e34 Add hacky hand-made carry/save multiplier - will improve James E. Stine 2021-10-16 10:37:29 -0500
  • c34633804a cvtfp module documented Katherine Parry 2021-10-14 15:25:31 -0700
  • c5b99300e7 Clean up some signals - beautification onging James E. Stine 2021-10-14 17:12:00 -0500
  • 869c35ba1c Fixed typo in imperas64mmu tests causing PMP tests not to run. Kip Macsai-Goren 2021-10-14 13:42:24 -0700
  • 71397d5db9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Skylar Litz 2021-10-13 15:38:32 -0700
  • 4ca4e13ba2 add StallM signal back to DivStartE control Skylar Litz 2021-10-13 15:34:40 -0700
  • 1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to individual regression test for TestFloat (still needs some tweaking) James E. Stine 2021-10-13 17:14:42 -0500
  • a898204c04 added outputs from synth run to test mul changes kipmacsaigoren 2021-10-13 12:38:14 -0500
  • bfe972a213 gitignore new logs folder bbracker 2021-10-12 10:42:13 -0700
  • 4abc6fc915 change infrastructure to expect only 6.3 million from buildroot bbracker 2021-10-12 10:41:15 -0700
  • 4424006624 added DESIGN_COMPLIER to forgotten config files Shreya Sanghai 2021-10-12 10:14:04 -0700
  • b79021a73e lint warnings fixed Katherine Parry 2021-10-12 09:45:02 -0700
  • 539d21645f some fpu lint warnings fixed - still working on it Katherine Parry 2021-10-11 18:32:03 -0700
  • 7873ba7867 added historical outputs folder for synth runs kipmacsaigoren 2021-10-11 19:52:52 -0500
  • f6c6cb9ed2 Merge branch 'main' into fpga Ross Thompson 2021-10-11 18:17:58 -0500
  • b3694bfdfd Fixed boot loader program to start at correct address. modified script which converts the ram.txt into preload text file for sdc simulation. created script to convert ram.txt into binary to write to flash card. added top level for solo sd card fpga. Ross Thompson 2021-10-11 17:22:23 -0500
  • 0acf9fd746 made redunantmul generate DW02_multp for synopsys sythnesis Shreya Sanghai 2021-10-11 11:54:39 -0700
  • 84ff2b49c7 actually added redundant mul Shreya Sanghai 2021-10-11 11:28:19 -0700
  • af7903e1b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-11 11:21:39 -0700
  • 1cdc5db75d Extended lint to check rv32/64g (including fpu. Not clean yet. David Harris 2021-10-11 11:20:42 -0700
  • a1c9ffdf2b added redundant multiplier Shreya Sanghai 2021-10-11 11:20:12 -0700
  • ab6a796690 Starting to optimize multiplier David Harris 2021-10-11 11:06:07 -0700
  • f1eda1bf6f Fixed sdc byte and nibble orders. Ross Thompson 2021-10-11 12:15:52 -0500
  • 76e186693c Update README.md davidharrishmc 2021-10-11 08:50:44 -0700
  • 9150133c7d Fpga simualtion files. Ross Thompson 2021-10-11 10:24:40 -0500
  • bfe633d087 Partially working sd card reader. Ross Thompson 2021-10-11 10:23:45 -0500
  • 8a39f37f94 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-11 08:14:38 -0700
  • f1190b6ceb intdiv cleanup David Harris 2021-10-11 08:14:21 -0700
  • fa2c6bf381 Update README.md davidharrishmc 2021-10-11 08:13:15 -0700
  • 4139f27d10 Divider FSM simplification David Harris 2021-10-10 22:24:14 -0700
  • 75c17dc372 Major reorganization of regression and simulation and testbenches David Harris 2021-10-10 15:07:51 -0700
  • 2b66615812 Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH James E. Stine 2021-10-10 15:44:01 -0500
  • 13352eccda Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-10-10 13:12:44 -0700
  • 161767cddd make regression expect what buildroot is actually able to reach bbracker 2021-10-10 13:12:36 -0700
  • a6c6b2b974 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-10 12:26:15 -0700
  • caf3c2de9b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-10-10 12:25:11 -0700