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  • 85d510e315 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-02-01 10:50:38 -0600
  • 6c3109287d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-02-01 10:50:24 -0600
  • 73edd50120 Updated fpga's bootloader to reflect the changes to the gpio address change. Ross Thompson 2022-02-01 10:43:24 -0600
  • 9770fbac70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-31 22:58:37 +0000
  • 96a0baade4 Removed soc_flow David Harris 2022-01-31 22:58:33 +0000
  • 2b71d48160 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-31 16:32:24 -0600
  • 1f0821da0d IFU and LSU now share the same busdp module. Ross Thompson 2022-01-31 16:25:41 -0600
  • 86bac2a083 partial ifu cleanup. Ross Thompson 2022-01-31 13:48:14 -0600
  • 4b94cf9a43 Renamed test library Kip Macsai-Goren 2022-01-31 20:11:03 +0000
  • 4d951923f4 updated minfo test to account for no mconfigptr Kip Macsai-Goren 2022-01-31 20:04:58 +0000
  • 14933a7231 fixed CSR read-only test to have correct output Kip Macsai-Goren 2022-01-31 20:03:00 +0000
  • e4ee630a3e cleanup. Ross Thompson 2022-01-31 13:16:23 -0600
  • 5ce8dd60c5 Fixed modelsim warning with linux simulation. Ross Thompson 2022-01-31 12:57:02 -0600
  • c9a163b8fd Repaired linux-wave.do Ross Thompson 2022-01-31 12:54:18 -0600
  • 4422e2f91c Repaired wavefile and fixed modelsim warning. Ross Thompson 2022-01-31 12:34:17 -0600
  • c2b2fae98d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-31 12:17:37 -0600
  • f4e62bcb54 Cleanup busdp. Ross Thompson 2022-01-31 12:11:42 -0600
  • 31da37dd0f Moved lsu virtual memory logic into separate module. Ross Thompson 2022-01-31 11:56:03 -0600
  • 9cd502d0af Encapsulated dtim. Ross Thompson 2022-01-31 10:51:06 -0600
  • c939eb20eb Removed unused signals in the LSU. Ross Thompson 2022-01-31 10:35:35 -0600
  • 5fe30ff8a9 Moved atomic logic to own module. Ross Thompson 2022-01-31 10:28:12 -0600
  • a4f6653cd8 Encapsulated the bus data path into a separate module. Ross Thompson 2022-01-31 10:11:58 -0600
  • 242b27705d added machine info test that uses new test library Kip Macsai-Goren 2022-01-31 05:54:25 +0000
  • 3c61d6eec2 tentatively remade test lib to use macros for more flexibility Kip Macsai-Goren 2022-01-31 05:53:36 +0000
  • ee982c7588 converted library to header file for RISCV test compliance Kip Macsai-Goren 2022-01-30 23:08:02 +0000
  • 9e3b25c940 updated tests to use test title instead of number encoding Kip Macsai-Goren 2022-01-30 22:56:03 +0000
  • d4ea8c6ac1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main James Stine 2022-01-30 21:03:24 -0600
  • 2405454c85 Change DC script to not do a full synthesis but partial synthesis until I configure to be more optimized James Stine 2022-01-30 21:02:41 -0600
  • 090533cfe9 Replaced || and && with | and & David Harris 2022-01-31 01:07:35 +0000
  • 3016b46d65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-31 00:59:49 +0000
  • 71f7d66dbf gitmodules David Harris 2022-01-31 00:59:44 +0000
  • af8aa56a67 Add synthesis using DC shell back into repository James Stine 2022-01-30 17:35:15 -0600
  • 00619eda07 Add synthesis using DC shell back into repository James Stine 2022-01-30 17:34:56 -0600
  • ac50a36aac LSU and IFU cleanup. Ross Thompson 2022-01-28 15:26:06 -0600
  • 2e00186eea Updated wave.do to match the ifu/lsu changes. Ross Thompson 2022-01-28 14:27:11 -0600
  • 42d60235f0 Clean up of mmu instances in IFU and LSU. Ross Thompson 2022-01-28 14:02:05 -0600
  • c5e0024e9f Moved spills to own module. Ross Thompson 2022-01-28 13:40:02 -0600
  • 06209c417f Cleaned up the InstrMisalignedFault. Ross Thompson 2022-01-28 13:19:24 -0600
  • 3b31d8f8fb Updated debug2 ila signal names. Ross Thompson 2022-01-28 11:43:49 -0600
  • 8fd975da74 Remove book_flow to add back later - will add synthDC back within 30m James Stine 2022-01-28 08:18:30 -0600
  • 6dfeade41b Added math.h to fir.c David Harris 2022-01-28 00:26:06 +0000
  • 862bf2faae Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. Ross Thompson 2022-01-27 17:11:27 -0600
  • d15cb64bdf Relocated the misalignment faults. Ross Thompson 2022-01-27 16:03:00 -0600
  • 30cc27e719 IFU cleanup David Harris 2022-01-27 17:18:55 +0000
  • 5ab06fef20 IFU cleanup David Harris 2022-01-27 16:41:57 +0000
  • bdd5796f3a Optimized out second adder from IFU for PC+2 David Harris 2022-01-27 16:06:24 +0000
  • 7f91170bab Comments in LSU code about restructuring David Harris 2022-01-27 15:53:59 +0000
  • b44f57b6b5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-27 08:45:33 -0600
  • 284d671da3 Increased number of concurrent tests. Ross Thompson 2022-01-27 08:45:25 -0600
  • 448acedd8b Set up rv32emc config David Harris 2022-01-27 14:37:58 +0000
  • 2b1aa9cada Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-27 14:33:35 +0000
  • 064a02de18 Added synthesis submodules David Harris 2022-01-27 14:31:34 +0000
  • 25c8c45a70 Added generated source code for the wally riscv arch tests rv32i_m and rv64i_m. Ross Thompson 2022-01-27 08:11:46 -0600
  • db0a0bd29e BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. Ross Thompson 2022-01-27 07:59:59 -0600
  • 3ebcd35a8c Added colors to regression script to make it easy to pick out success from fail. Ross Thompson 2022-01-26 22:40:32 -0600
  • cc5a9a015b Removed mux in PCNextF logic. Minor IFU improvements. Ross Thompson 2022-01-26 22:33:26 -0600
  • 42ef1e22e5 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 2. Removed the write address delay from simpleram.sv 3. Fixed rv32tim and rv32ic mode to handle missalignment correctly. 4. Added imperas32i and imperas32c to rv32tim mode. Ross Thompson 2022-01-26 17:37:04 -0600
  • fc86651937 IFU simplifications. Ross Thompson 2022-01-26 13:54:59 -0600
  • b359499820 Adjusted test cases for new GPIO base address David Harris 2022-01-26 19:15:48 +0000
  • 748375c82f Updated configs to fix GPIO address to match FU540 David Harris 2022-01-26 18:16:34 +0000
  • 21bdce63ff Testgen working for Lab 2 David Harris 2022-01-26 18:01:51 +0000
  • 4d788505f2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-26 17:21:09 +0000
  • e16982aeb0 New testgen.py David Harris 2022-01-26 17:21:02 +0000
  • 676d4c5fa7 a different approach to QEMU: add Wally as a completely new machine bbracker 2022-01-26 15:02:24 +0000
  • 840e814e95 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-25 19:21:04 -0600
  • d46bc94119 Added pin location for reset on VCU118 board. Somehow this was missing and still worked. Ross Thompson 2022-01-25 17:48:42 -0600
  • 3a7786877a Removed and restored embench-iot David Harris 2022-01-25 22:12:28 +0000
  • bb11f5637c Added comport.setup to remind how to configure com port for xilinx fpga. Added load-deadlock.tsm to trigger load operation deadlock. Ross Thompson 2022-01-25 14:54:38 -0600
  • 8d04e83c9f simpleram simplification David Harris 2022-01-25 19:46:13 +0000
  • 9da1ed4ed9 simpleram simplification David Harris 2022-01-25 19:40:07 +0000
  • a86a9f5c2a simpleram simplification David Harris 2022-01-25 18:26:31 +0000
  • e3136c9a1e simpleram address simplification David Harris 2022-01-25 18:17:33 +0000
  • 7ad2eb009a simpleram address simplification David Harris 2022-01-25 18:00:50 +0000
  • 6a555032eb simpleram clk and reset simplification David Harris 2022-01-25 17:34:15 +0000
  • cf50beb958 Start of IFU cleanup David Harris 2022-01-25 17:31:53 +0000
  • 99a824fdc1 removed sum executable David Harris 2022-01-25 10:24:05 +0000
  • 8d83b3b722 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-25 06:53:07 +0000
  • 2bc7399ad4 More example Makefile cleanup David Harris 2022-01-25 06:53:03 +0000
  • f6a27588f3 Update README.md davidharrishmc 2022-01-24 15:47:42 -0800
  • 544b9273c2 Update README.md davidharrishmc 2022-01-24 15:46:24 -0800
  • 2dc73574d3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-24 23:21:16 +0000
  • 12e08d8055 Fixed sumtest reference output; added embench benchmark directory David Harris 2022-01-24 23:21:09 +0000
  • b0cbe9dba8 added qemu patches in tests/linux-testgen/qemu kaveh Pezeshki 2022-01-24 07:52:07 +0000
  • 8ef70389d3 Added spill support back into the IROM IFU. Ross Thompson 2022-01-21 15:50:54 -0600
  • 9982549057 Changed the IROM and DTIM memories to behave like edge-triggered srams. Ross Thompson 2022-01-21 15:42:54 -0600
  • 0ceaf792ed erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-21 00:12:18 +0000
  • 39d318fb2a Fixed path to riscvOVPsimPlus David Harris 2022-01-21 00:12:14 +0000
  • e2343699d1 Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv Ross Thompson 2022-01-20 16:39:54 -0600
  • 57f859a882 fir.c David Harris 2022-01-20 17:15:53 +0000
  • 771c44698b Added FIR example David Harris 2022-01-20 16:57:36 +0000
  • 07425369fc Renamed wallypipelinedhart to wallypipelinedcore David Harris 2022-01-20 16:02:08 +0000
  • cea09aab98 Removed imperas tests from makefile for now David Harris 2022-01-20 14:51:56 +0000
  • fc932ef0ff Added top-level make clean David Harris 2022-01-20 14:17:26 +0000
  • d5f12195c8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-20 00:04:27 +0000
  • 3005d82dba Created linux directory for linux config David Harris 2022-01-20 00:04:23 +0000
  • acec56c27e Added PCNextF and PostSpillInstrRawF to ila. Ross Thompson 2022-01-19 14:05:14 -0600
  • c913a3ceeb Fixed fpga ila debug to match lsu changes. Ross Thompson 2022-01-18 21:13:18 -0600
  • 9b29710990 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-19 00:26:34 +0000
  • 4a75e69457 Merged in the debug ila updates. Ross Thompson 2022-01-18 17:29:21 -0600
  • 28859f959b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-18 17:19:59 -0600