forked from Github_Repos/cvw
Adjusted test cases for new GPIO base address
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@ -47,7 +47,7 @@ _start:
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# write to gpio
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li x2, 0xFF
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la x3, 0x10012000
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la x3, 0x10060000
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# +8 is output enable
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# +C is output value
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@ -47,7 +47,7 @@ _start:
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# write to gpio
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li x2, 0xFF
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la x3, 0x10012000
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la x3, 0x10060000
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# +8 is output enable
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# +C is output value
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@ -71,7 +71,7 @@ copy_sdc2:
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# write to gpio
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li x2, 0xFF
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la x3, 0x10012000
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la x3, 0x10060000
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# +8 is output enable
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# +C is output value
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@ -27,7 +27,7 @@
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#define RAM_RANGE 0x7FFFFFFF
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#define CLINT_BASE 0x02000000
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#define CLINT_RANGE 0x0000FFFF
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#define GPIO_BASE 0x10012000
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#define GPIO_BASE 0x10060000
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#define GPIO_RANGE 0x000000FF
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#define UART_BASE 0x10000000
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#define UART_RANGE 0x00000007
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@ -27,7 +27,7 @@
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#define RAM_RANGE 0x7FFFFFFF
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#define CLINT_BASE 0x02000000
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#define CLINT_RANGE 0x0000FFFF
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#define GPIO_BASE 0x10012000
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#define GPIO_BASE 0x10060000
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#define GPIO_RANGE 0x000000FF
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#define UART_BASE 0x10000000
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#define UART_RANGE 0x00000007
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