forked from Github_Repos/cvw
Add synthesis using DC shell back into repository
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James Stine
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00619eda07
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#
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# Main Synopsys Flow
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# james.stine@okstate.edu 26 Jan 2022
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#
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# Config
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set hdl_src "../pipelined/src"
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eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/}
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eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/}
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eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
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eval file copy [glob ${hdl_src}/*/*.sv] {hdl/}
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eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/}
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# Verilog files
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set my_verilog_files [glob hdl/*]
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# Set toplevel
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set my_toplevel wallypipelinedcore
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# Set number of significant digits
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set report_default_significant_digits 6
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# V(HDL) Unconnectoed Pins Output
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set verilogout_show_unconnected_pins "true"
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set vhdlout_show_unconnected_pins "true"
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#
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# Due to parameterized Verilog must use analyze/elaborate and not
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# read_verilog/vhdl (change to pull in Verilog and/or VHDL)
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#
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define_design_lib WORK -path ./WORK
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analyze -f sverilog -lib WORK $my_verilog_files
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#
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# Added if you had any VHDL
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# analyze -f vhdl -lib WORK $my_vhdl_files
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#
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elaborate $my_toplevel -lib WORK
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# Set the current_design
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current_design $my_toplevel
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link
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# Reset all constraints
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reset_design
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# Set Frequency in [MHz] or [ps]
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set my_clock_pin clk
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set my_clk_freq_MHz 25
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set my_period [expr 1000 / $my_clk_freq_MHz]
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set my_uncertainty [expr .1 * $my_period]
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# Create clock object
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set find_clock [ find port [list $my_clock_pin] ]
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if { $find_clock != [list] } {
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echo "Found clock!"
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set my_clk $my_clock_pin
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create_clock -period $my_period $my_clk
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set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
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} else {
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echo "Did not find clock! Design is probably combinational!"
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set my_clk vclk
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create_clock -period $my_period -name $my_clk
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}
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# Partitioning - flatten or hierarchically synthesize
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#ungroup -flatten -simple_names { dp* }
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#ungroup -flatten -simple_names { c* }
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#ungroup -all -flatten -simple_names
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# Set input pins except clock
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set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
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# Specifies delays be propagated through the clock network
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set_propagated_clock [get_clocks $my_clk]
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# Setting constraints on input ports
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set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk
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# Set input/output delay
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set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
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set_output_delay 0.0 -max -clock $my_clk [all_outputs]
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# Setting load constraint on output ports
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set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs]
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# Set the wire load model
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set_wire_load_mode "top"
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# Attempt Area Recovery - if looking for minimal area
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# set_max_area 2000
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# Set fanout
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set_max_fanout 6 $all_in_ex_clk
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# Fix hold time violations
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set_fix_hold [all_clocks]
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# Deal with constants and buffers to isolate ports
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set_fix_multiple_port_nets -all -buffer_constants
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# setting up the group paths to find out the required timings
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#group_path -name OUTPUTS -to [all_outputs]
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#group_path -name INPUTS -from [all_inputs]
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#group_path -name COMBO -from [all_inputs] -to [all_outputs]
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# Save Unmapped Design
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set filename [format "%s%s%s" "unmapped/" $my_toplevel ".ddc"]
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write_file -format ddc -hierarchy -o $filename
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# Compile statements - either compile or compile_ultra
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compile -scan -incr -map_effort high
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# compile_ultra -no_seq_output_inversion -no_boundary_optimization
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# Eliminate need for assign statements (yuck!)
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set verilogout_no_tri true
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set verilogout_equation false
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# setting to generate output files
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set write_v 1 ;# generates structual netlist
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set write_sdc 1 ;# generates synopsys design constraint file for p&r
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set write_ddc 1 ;# compiler file in ddc format
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set write_sdf 1 ;# sdf file for backannotated timing sim
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set write_pow 1 ;# genrates estimated power report
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set write_rep 1 ;# generates estimated area and timing report
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set write_cst 1 ;# generate report of constraints
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set write_hier 1 ;# generate hierarchy report
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# Report Constraint Violators
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set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint_all_violators.rpt"]
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redirect $filename {report_constraint -all_violators}
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# Check design
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redirect reports/check_design.rpt { check_design }
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# Report Final Netlist (Hierarchical)
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".vh"]
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write_file -f verilog -hierarchy -output $filename
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdc"]
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write_sdc $filename
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".ddc"]
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write_file -format ddc -hierarchy -o $filename
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set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdf"]
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write_sdf $filename
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# QoR
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set filename [format "%s%s%s" "reports/" $my_toplevel "_qor.rep"]
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redirect $filename { report_qor }
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# Report Timing
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set filename [format "%s%s%s" "reports/" $my_toplevel "_reportpath.rep"]
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redirect $filename { report_path_group }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_report_clock.rep"]
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redirect $filename { report_clock }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_timing.rep"]
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redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_min_timing.rep"]
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redirect $filename { report_timing -delay min }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_area.rep"]
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redirect $filename { report_area -hierarchy -nosplit -physical -designware}
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set filename [format "%s%s%s" "reports/" $my_toplevel "_cell.rep"]
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redirect $filename { report_cell [get_cells -hier *] }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_power.rep"]
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redirect $filename { report_power }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint.rep"]
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redirect $filename { report_constraint }
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set filename [format "%s%s%s" "reports/" $my_toplevel "_hier.rep"]
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redirect $filename { report_hierarchy }
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# Quit
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quit
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