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528 Commits

Author SHA1 Message Date
bbracker
a88ae5aaff use correct string formatting function 2021-10-10 10:09:59 -07:00
bbracker
6fce53d146 make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00
Kip Macsai-Goren
303beaa083 updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully. 2021-10-08 15:40:18 -07:00
David Harris
3d0383c154 moved fp vectors into vectors subdirectory 2021-10-07 23:28:06 -04:00
David Harris
6dd85b80a2 Included TestFloat and SoftFloat 2021-10-07 23:03:45 -04:00
James E. Stine
28e147bb19 update scripts 2021-10-07 15:14:54 -05:00
James E. Stine
8429078d4f TV for conversion and compare 2021-10-06 14:38:32 -05:00
James E. Stine
93668b5185 Update to testbench for FP stuff 2021-10-06 13:16:38 -05:00
James E. Stine
2afa6e7a6e Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included 2021-10-06 08:56:01 -05:00
Skylar Litz
5bcae393c9 added delayed MIP signal 2021-10-04 18:23:31 -04:00
David Harris
48e33c79a9 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
2ae51d1852 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
fbe6e41169 Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
e11c565a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit fec96218f6.
 2021-09-30 20:45:26 -04:00
David Harris
caa36f267d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
42d573be57 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
fec96218f6 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
bbracker
7117c0493c condense testbench code; debug_level of 0 means don't check at all 2021-09-27 03:03:11 -04:00
bbracker
3f96ff0ac0 switch testbench-linux's interrupts from xcause to mip and improve warning messages 2021-09-22 12:33:11 -04:00
bbracker
ff5379fd95 fix regression 2021-09-15 17:30:59 -04:00
David Harris
92385a1d51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-13 12:41:07 -04:00
David Harris
9fa048980d Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
Ross Thompson
cd6d1e0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-13 09:41:34 -05:00
David Harris
7be1160a48 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
Ross Thompson
296da4f437 FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
David Harris
12bd351edf Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
6550f38af9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
bbracker
bb84354a47 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
bbracker
f8272c45d1 make testbench successfully deactivate TimerIntM so as to create a nice pulse 2021-09-07 15:36:47 -04:00
bbracker
da9a366d20 No longer forcing CSRReadValM because that can feedback to corrupt some CSRs 2021-09-06 22:59:54 -04:00
bbracker
b3bc3cf6d0 modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations) 2021-09-04 19:49:26 -04:00
Ross Thompson
86fc632790 Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
e9a1dc90f6 Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
fe378f2692 Added function tracking to linux test bench. 2021-08-24 11:08:46 -05:00
Ross Thompson
c31b7b4dc5 Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
2825074114 Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
Ross Thompson
6c57002d0e Added logic to linux test bench to not stop simulation on csr write faults. 2021-08-15 11:13:32 -05:00
Ross Thompson
55fda4de62 Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Ross Thompson
32db21659f Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token. 2021-08-13 14:53:43 -05:00
Ross Thompson
e141a00934 Cleaned up the linux testbench by removing old code and signals. 
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
 2021-08-13 14:39:05 -05:00
Ross Thompson
9ff9c4dff9 Minor cleanup of the linux test bench. 2021-08-12 11:14:55 -05:00
Ross Thompson
cce0571925 Fixed another bug with the atomic instrucitons implemention in the dcache. 2021-08-08 22:50:31 -05:00
Ross Thompson
fc7016eea6 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
 2021-08-08 00:28:18 -05:00
Ross Thompson
aa9a5d879b Finally past the CLINT issues. 2021-08-06 16:41:34 -05:00
Ross Thompson
0bfbcef8ab Now past the CLINT issues. 2021-08-06 16:16:39 -05:00
Ross Thompson
9be10cdc8b Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts. 2021-08-06 16:06:50 -05:00
Ross Thompson
c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Ross Thompson
3582be4dbb Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction. 2021-08-05 16:49:03 -05:00
Ross Thompson
f808b29065 Added some comments to linux testbench. 2021-07-30 17:57:03 -05:00
Ross Thompson
e166cc84ee Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files. 2021-07-30 14:24:50 -05:00
Ross Thompson
74fba4bb06 Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
Ross Thompson
d8878581f4 Created new linux test bench and parsing scripts. 2021-07-29 20:26:50 -05:00
Kip Macsai-Goren
3008111bcd added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet 2021-07-23 16:02:42 -04:00
Kip Macsai-Goren
381a93b45b added sfence to legal instructions, zeroed out rom file to populate for tests 2021-07-23 15:55:08 -04:00
Kip Macsai-Goren
da9ead2d95 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-23 15:16:01 -04:00
bbracker
0e64b99dc0 testbench workaround for QEMU's SSTATUS XLEN bits 2021-07-23 14:00:44 -04:00
Kip Macsai-Goren
52faa22774 include SFENCE.VMA in legal instructions 2021-07-22 20:24:24 -04:00
David Harris
21a65f45cd Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
bbracker
cca16cc5b4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-21 20:07:03 -04:00
bbracker
6e460c5032 replace physical address checking with virtual address checking because address translator is broken 2021-07-21 19:47:13 -04:00
Katherine Parry
01f0b4e5df FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
Katherine Parry
b9081e514c FMA parameterized 2021-07-20 22:04:21 -04:00
bbracker
f9b6bd91f5 fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk 2021-07-20 17:55:44 -04:00
bbracker
a02694a529 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 15:04:13 -04:00
bbracker
a3823ce3a9 commented out old hack that used hardcoded addresses 2021-07-20 15:03:55 -04:00
David Harris
e5e3f5abe6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 14:46:58 -04:00
David Harris
1f3dfa20f6 flag for optional boottim 2021-07-20 14:46:37 -04:00
bbracker
6b72b1f859 ignore mhpmcounters because QEMU doesn't implement them 2021-07-20 13:37:52 -04:00
bbracker
a1ea654b11 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 12:08:46 -04:00
David Harris
e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
bbracker
9e658466e6 testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr) 2021-07-20 05:40:39 -04:00
bbracker
3b10ea9785 major fixes to CSR checking 2021-07-20 00:22:07 -04:00
bbracker
c1d63fe77c MemRWM shouldn't factor into PCD checking 2021-07-19 18:03:30 -04:00
bbracker
f7d040af1e make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways 2021-07-19 17:11:42 -04:00
bbracker
65df5c087b adapt testbench to removal of ReadDataWEn signal 2021-07-19 15:42:14 -04:00
bbracker
ae5663a244 adapt testbench to removal of signal 2021-07-19 15:41:50 -04:00
bbracker
cd469035be make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset 2021-07-19 15:13:03 -04:00
Katherine Parry
c9180f4ebd FDIV and FSQRT passes when simulating in modelsim 2021-07-18 23:00:04 -04:00
bbracker
5e9dcb3f1c linux testbench progress 2021-07-18 18:47:40 -04:00
Katherine Parry
60dabb9094 fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
Ross Thompson
14220684b6 Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue. 2021-07-17 21:02:24 -05:00
David Harris
8d348dacce Started atomics 2021-07-17 21:11:41 -04:00
bbracker
82fc766819 swapped out linux testbench signal names 2021-07-17 14:48:12 -04:00
David Harris
87aa527de7 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ef63e1ab52 hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
dac22d5016 Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
Kip Macsai-Goren
d10fd25c33 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
5e18a15a4c Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00