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make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways

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bbracker 2021-07-19 17:11:42 -04:00
parent f17f6cea56
commit f7d040af1e
1 changed files with 3 additions and 1 deletions
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wally-pipelined/testbench/testbench-linux.sv
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@ -530,6 +530,7 @@ module testbench();
// Checker Macros
// --------------
string MSTATUSstring = "MSTATUS"; // string variables seem to compare more reliably than string literals (they gave me a lot of hassle), but *** there's probably a better way to do this
string MIPstring = "MIP";
string SEPCstring = "SEPC";
string SCAUSEstring = "SCAUSE";
string SSTATUSstring = "SSTATUS";
@ -539,7 +540,8 @@ module testbench();
string ``CSR``name = `"CSR`"; \
string expected``CSR``name; \
always @(``PATH``.``CSR``_REGW) begin \
if ($time > 1 && (`BUILDROOT != 1 || ``CSR``name != SSTATUSstring)) begin \
// MIP is not checked because QEMU bodges it (MTIP in particular), and even if QEMU reported it correctly, the timing would still be off \
if ($time > 1 && (``CSR``name != MIPstring)) begin \
// This is some feeble hackery designed to control the order in which CSRs are checked \
// when multiple change at the same time. \
if (``CSR``name == SEPCstring) #1; \