forked from Github_Repos/cvw
major fixes to CSR checking
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@ -27,7 +27,7 @@
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module testbench();
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0459700; // # of instructions at which to turn on waves in graphical sim
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0675000; // # of instructions at which to turn on waves in graphical sim
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parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
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///////////////////////////////////////////////////////////////////////////////
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@ -103,6 +103,7 @@ module testbench();
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logic [99:0] StartCSRexpected[63:0];
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string StartCSRname[99:0];
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integer data_file_csr, scan_file_csr;
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logic IllegalInstrFaultd;
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// -----------
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// Error Macro
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@ -158,16 +159,11 @@ module testbench();
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// -------------------------------------
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always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin
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if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs > 1) begin
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$display("!!!!!! illegal instruction !!!!!!!!!!");
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$display("(as a reminder, MCAUSE and MEPC are set by this)");
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$display("at %0t ps, PCM %x, instr %0d, dut.hart.lsu.dcache.MemPAdrM %x", $time, dut.hart.ifu.PCM, instrs, dut.hart.lsu.dcache.MemPAdrM);
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`ERROR
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// This is sometimes okay if the source code intentionally causes it.
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$display("Warning: illegal instruction exception at %0t ps, InstrNum %0d, PCM %x, InstrM %s", $time, instrs, dut.hart.ifu.PCM, PCtextM);
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end
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if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin
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$display("!!!!!! illegal (physical) memory access !!!!!!!!!!");
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$display("(as a reminder, MCAUSE and MEPC are set by this)");
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$display("at %0t ps, PCM %x, instr %0d, dut.hart.lsu.dcache.MemPAdrM %x", $time, dut.hart.ifu.PCM, instrs, dut.hart.lsu.dcache.MemPAdrM);
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`ERROR
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$display("Warning: illegal physical memory access exception at %0t ps, InstrNum %0d, PCM %x, InstrM %s", $time, instrs, dut.hart.ifu.PCM, PCtextM);
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end
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end
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@ -524,50 +520,70 @@ module testbench();
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end
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end
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// -------------------
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// Additional Hardware
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// -------------------
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always @(posedge clk)
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IllegalInstrFaultd = dut.hart.priv.IllegalInstrFaultM;
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// --------------
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// Checker Macros
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// --------------
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string MSTATUSstring = "MSTATUS"; // string variables seem to compare more reliably than string literals (they gave me a lot of hassle), but *** there's probably a better way to do this
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// String variables seem to compare more reliably than string literals (they gave me a lot of hassle),
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// but *** there's probably a better way to do this.
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// You can't just use the "__name" variables though because you need to declare variables before using them.
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string MSTATUSstring = "MSTATUS";
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string MIPstring = "MIP";
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string MEPCstring = "MEPC";
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string MCAUSEstring = "MCAUSE";
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string MTVALstring = "MTVAL";
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string SEPCstring = "SEPC";
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string SCAUSEstring = "SCAUSE";
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string SSTATUSstring = "SSTATUS";
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logic [63:0] expectedCSR;
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string expectedCSRname;
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`define CHECK_CSR2(CSR, PATH) \
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logic [63:0] expected``CSR``; \
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string CSR; \
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string ``CSR``name = `"CSR`"; \
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string expected``CSR``name; \
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always @(``PATH``.``CSR``_REGW) begin \
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// MIP is not checked because QEMU bodges it (MTIP in particular), and even if QEMU reported it correctly, the timing would still be off \
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if ($time > 1 && (``CSR``name != MIPstring)) begin \
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// This is some feeble hackery designed to control the order in which CSRs are checked \
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// when multiple change at the same time. \
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if (``CSR``name == SEPCstring) #1; \
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if (``CSR``name == SCAUSEstring) #2; \
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if (``CSR``name == SSTATUSstring) #3; \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", expected``CSR``name); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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if(expected``CSR``name.icompare(``CSR``name)) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s changed, expected %s", $time, dut.hart.ifu.PCM, PCtextM, instrs, `"CSR`", expected``CSR``name); \
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if (instrs == 0 && ~reset) begin \
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for(integer j=0; j<totalCSR; j++) begin \
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if(!StartCSRname[j].icompare(``CSR``name)) begin \
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if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s does not equal %s expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, ``CSR``name, StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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`ERROR \
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end \
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end \
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end \
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if (``CSR``name == MSTATUSstring) begin \
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if (``PATH``.``CSR``_REGW != ((``expected``CSR) | 64'ha00000000)) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s (should be MSTATUS) does not equal %s expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, ``CSR``name, expected``CSR``name, ``PATH``.``CSR``_REGW, (``expected``CSR) | 64'ha00000000); \
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`ERROR \
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end \
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end else \
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if (``PATH``.``CSR``_REGW != ``expected``CSR[$bits(``PATH``.``CSR``_REGW)-1:0]) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s does not equal %s expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, ``CSR``name, expected``CSR``name, ``PATH``.``CSR``_REGW, ``expected``CSR); \
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`ERROR \
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end \
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$display("CSRs' intital states look good"); \
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end else begin \
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if (!(`BUILDROOT == 1 && ``CSR``name == MSTATUSstring)) begin \
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for(integer j=0; j<totalCSR; j++) begin \
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if(!StartCSRname[j].icompare(``CSR``name)) begin \
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if(``PATH``.``CSR``_REGW != StartCSRexpected[j]) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s does not equal %s expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, ``CSR``name, StartCSRname[j], ``PATH``.``CSR``_REGW, StartCSRexpected[j]); \
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`ERROR \
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end \
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// MIP is not checked because QEMU bodges it (MTIP in particular), and even if QEMU reported it correctly, the timing would still be off \
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// MTVAL is not checked on illegal instr faults because QEMU chooses not to implement the behavior where MTVAL is written with the faulting instruction \
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if (~reset && ``CSR``name != MIPstring && ~(IllegalInstrFaultd && ``CSR``name == MTVALstring)) begin \
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// This is some feeble hackery designed to control the order in which CSRs are checked \
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// when multiple change at the same time. \
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// *** it would be better for each CSR to have its own testvector file \
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// so as to avoid this awkward ordering problem. \
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if (``CSR``name == MEPCstring) #1; \
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if (``CSR``name == MCAUSEstring) #2; \
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if (``CSR``name == MTVALstring) #3; \
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if (``CSR``name == SEPCstring) #1; \
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if (``CSR``name == SCAUSEstring) #2; \
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if (``CSR``name == SSTATUSstring) #3; \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", expectedCSRname); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expectedCSR); \
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if(expectedCSRname.icompare(``CSR``name)) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s changed, expected %s", $time, dut.hart.ifu.PCM, PCtextM, instrs, `"CSR`", expectedCSRname); \
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end \
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if (``CSR``name == MSTATUSstring) begin \
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if (``PATH``.``CSR``_REGW != ((expectedCSR) | 64'ha00000000)) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s (should be MSTATUS) does not equal %s expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, ``CSR``name, expectedCSRname, ``PATH``.``CSR``_REGW, expectedCSR | 64'ha00000000); \
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`ERROR \
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end \
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end else begin \
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if (``PATH``.``CSR``_REGW != expectedCSR[$bits(``PATH``.``CSR``_REGW)-1:0]) begin \
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$display("%0t ps, PCM %x %s, instr %0d: %s does not equal %s expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, ``CSR``name, expectedCSRname, ``PATH``.``CSR``_REGW, expectedCSR); \
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`ERROR \
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end \
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end \
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end \
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