forked from Github_Repos/cvw
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
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@ -154,6 +154,12 @@ module testbench();
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clk <= 1; # 5; clk <= 0; # 5;
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end
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// -------------------
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// Additional Hardware
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// -------------------
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always @(posedge clk)
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IllegalInstrFaultd = dut.hart.priv.IllegalInstrFaultM;
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// -------------------------------------
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// Special warnings for important faults
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// -------------------------------------
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@ -181,8 +187,11 @@ module testbench();
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// Hack to compensate for QEMU's incorrect MSTATUS
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end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,16) == "mstatus") begin
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force dut.hart.ieu.dp.regf.wd3 = dut.hart.ieu.dp.WriteDataW & ~64'ha00000000;
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end else
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release dut.hart.ieu.dp.regf.wd3;
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end else release dut.hart.ieu.dp.regf.wd3;
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// Hack to compensate for QEMU's correct but different MTVAL (according to spec, storing the faulting instr is an optional feature)
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if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,14) == "mtval") begin
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force dut.hart.ieu.dp.WriteDataW = 0;
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end else release dut.hart.ieu.dp.WriteDataW;
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end
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end
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@ -200,7 +209,6 @@ module testbench();
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lastPC2 <= lastPC;
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// If PCD isn't going to be flushed
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if (~PCDwrong || lastPC == PCDexpected) begin
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// Stop if we've reached the end
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if($feof(data_file_PCF)) begin
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$display("no more PC data to read... CONGRATULATIONS!!!");
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@ -249,29 +257,7 @@ module testbench();
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// Check if PCD is going to be flushed due to a branch or jump
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if (`BPRED_ENABLED) begin
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PCDwrong = dut.hart.hzu.FlushD; //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET.
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end else begin
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casex (lastInstrDExpected[31:0])
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32'b00000000001000000000000001110011, // URET
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32'b00010000001000000000000001110011, // SRET
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32'b00110000001000000000000001110011, // MRET
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
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32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
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32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
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32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
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32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
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PCDwrong = 1;
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32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK:
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32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR*
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PCDwrong = 0; // tbh don't really know what should happen here
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32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, *
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32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
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32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
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PCDwrong = 1;
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default:
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PCDwrong = 0;
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endcase
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PCDwrong = dut.hart.hzu.FlushD || (PCtextE.substr(0,3) == "mret"); //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET.
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end
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// Check PCD, InstrD
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@ -354,9 +340,8 @@ module testbench();
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end
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`SCAN_PC(data_file_PCM, scan_file_PCM, trashString, trashString, InstrMExpected, PCMexpected);
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`SCAN_PC(data_file_PCW, scan_file_PCW, trashString, trashString, InstrWExpected, PCWexpected);
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// If repeated instr
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// If repeated or instruction, we want to skip over it (indicates an interrupt)
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if (PCMexpected == PCWexpected) begin
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// Increment file pointers past the repeated instruction.
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`SCAN_PC(data_file_PCM, scan_file_PCM, trashString, trashString, InstrMExpected, PCMexpected);
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`SCAN_PC(data_file_PCW, scan_file_PCW, trashString, trashString, InstrWExpected, PCWexpected);
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end
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@ -365,6 +350,11 @@ module testbench();
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`ERROR
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end
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end
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// Skip over faulting instructions because they do not make it to the W stage.
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if (IllegalInstrFaultd) begin
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`SCAN_PC(data_file_PCM, scan_file_PCM, trashString, trashString, InstrMExpected, PCMexpected);
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`SCAN_PC(data_file_PCW, scan_file_PCW, trashString, trashString, InstrWExpected, PCWexpected);
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end
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end
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@ -520,12 +510,6 @@ module testbench();
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end
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end
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// -------------------
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// Additional Hardware
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// -------------------
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always @(posedge clk)
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IllegalInstrFaultd = dut.hart.priv.IllegalInstrFaultM;
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// --------------
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// Checker Macros
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// --------------
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