David Harris
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4d509f94ec
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FDIV merge
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2022-12-22 23:03:03 -08:00 |
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David Harris
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2d72bed1f4
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Removed unused signals in FPU and CSR
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2022-12-22 22:59:05 -08:00 |
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Ross Thompson
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98b824c4c4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-22 22:51:33 -06:00 |
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Ross Thompson
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2cc4d66ded
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Renamed IFU and LSU stalls.
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2022-12-22 21:56:33 -06:00 |
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Ross Thompson
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03021765a6
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The LSU is properly using FlushW rather than TrapM.
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2022-12-22 21:47:34 -06:00 |
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Ross Thompson
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3b791b768a
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Success we've replaced TrapM with FlushD in the IFU.
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2022-12-22 21:36:49 -06:00 |
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Ross Thompson
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e0e92952c3
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Partial cleanup for BP.
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2022-12-22 20:33:38 -06:00 |
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Ross Thompson
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206bc7daa6
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Ross Thompson
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b1475df5e1
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Wavefile updates.
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2022-12-22 19:45:02 -06:00 |
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Kip Macsai-Goren
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ffae1c5ee6
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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a768d70093
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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7aadf50f26
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updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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Ross Thompson
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41fe876e7a
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First pass at resolving ifu flush on trap rather than FlushD.
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2022-12-22 15:53:06 -06:00 |
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David Harris
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d4bedca1bf
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Code cleanup
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2022-12-22 10:04:50 -08:00 |
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cturek
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ccbad67497
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Added negative-result int diviison support in U and UM registers. 13 tests pass!
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2022-12-22 16:25:37 +00:00 |
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cturek
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1b7ed72ece
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Moved swap from qslc to otfc
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2022-12-22 15:44:50 +00:00 |
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cturek
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3574bedb08
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-22 05:45:00 +00:00 |
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cturek
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80ca75e216
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Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
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2022-12-22 05:44:55 +00:00 |
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David Harris
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c42967f5c6
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XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 20:39:38 -08:00 |
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Ross Thompson
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c8c73f47d2
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CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
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2022-12-21 22:13:05 -06:00 |
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cturek
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0b4d81bd4a
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worked out some bugs with int div cycles
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2022-12-22 02:22:01 +00:00 |
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cturek
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c3fdc0ab23
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Renamed signals to E and M stages, forwarded preprocessed n to fsm
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2022-12-22 00:43:27 +00:00 |
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Ross Thompson
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84f8d9953f
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Updated cache fsm names to match book.
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2022-12-21 16:49:53 -06:00 |
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Ross Thompson
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d72cf65809
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 16:13:09 -06:00 |
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Ross Thompson
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e7a44d8975
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Changed GatedStallF to GatedStallD.
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2022-12-21 16:12:55 -06:00 |
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David Harris
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d0a3e939e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 14:12:25 -08:00 |
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David Harris
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8bc753a291
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Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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e5f7e68d31
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 14:57:19 -06:00 |
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Ross Thompson
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b7224cc5ba
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Updated fpga constraints.
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2022-12-21 14:50:01 -06:00 |
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cturek
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0c30ecf86d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-21 20:41:38 +00:00 |
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David Harris
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6d46261350
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comment cleanup
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2022-12-21 12:39:09 -08:00 |
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David Harris
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c7f3aae084
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Only delegated bits of SIP are readable
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2022-12-21 12:32:49 -08:00 |
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cturek
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ab71962dc0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-21 19:35:57 +00:00 |
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cturek
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c479b9f112
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fixed normshift calculations
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2022-12-21 19:35:47 +00:00 |
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David Harris
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5ef3a1d371
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git push
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 11:31:27 -08:00 |
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David Harris
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e327d70cdc
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Removed unused FPU signals
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2022-12-21 11:31:22 -08:00 |
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Ross Thompson
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c3b43b2fac
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Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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Ross Thompson
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0b4186f1e8
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Vectored interrupts now require 64 byte alignment.
Eliminates adder.
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2022-12-21 12:05:49 -06:00 |
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Ross Thompson
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91f948a91c
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The optimzied PC+2/4 logic still hanges on wally32priv.
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2022-12-21 09:19:34 -06:00 |
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Ross Thompson
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6858b7568c
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Renamed PCPlusUpperF to PCPlus4F.
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2022-12-21 09:18:30 -06:00 |
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Ross Thompson
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3d95aa3423
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Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
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2022-12-21 09:18:00 -06:00 |
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Ross Thompson
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ac94b55e74
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Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
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2022-12-21 09:00:09 -06:00 |
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Ross Thompson
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a02b40cf02
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Changes to wave file.
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2022-12-21 08:41:47 -06:00 |
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Ross Thompson
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fe723af1af
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Comments about PC+2/4.
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2022-12-21 08:35:43 -06:00 |
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David Harris
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5d91b3044f
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Clean up vecgtored interrupts
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2022-12-20 16:53:09 -08:00 |
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David Harris
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dd0a02f0c8
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Converted tvecmux to structural
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2022-12-20 16:24:04 -08:00 |
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Ross Thompson
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f860440361
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-20 18:09:37 -06:00 |
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Ross Thompson
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80be2e7be5
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privileged pc mux cleanup.
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2022-12-20 18:05:44 -06:00 |
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Ross Thompson
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97593e8a6f
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Moved privileged pc logic into privileged unit.
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2022-12-20 17:55:45 -06:00 |
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David Harris
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8f640f050f
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IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
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2022-12-20 15:38:30 -08:00 |
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