Cedar Turek
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ef360f0539
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idiv passing radix 2, four copies
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2022-12-27 22:11:18 -08:00 |
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Cedar Turek
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4ed2c6255c
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idiv passing radix 2, four copies
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2022-12-27 22:10:48 -08:00 |
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David Harris
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a832605658
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Moved IDIV for postproc into generate block
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2022-12-27 22:02:14 -08:00 |
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David Harris
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d59878a886
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Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc
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2022-12-27 21:53:00 -08:00 |
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Cedar Turek
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a559abe554
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Fixed cycles for multiple iterations. 2-copies radix 2 passing regression.
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2022-12-27 21:34:27 -08:00 |
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David Harris
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665b545fd0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-27 21:30:13 -08:00 |
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David Harris
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87abed6722
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cleanup
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2022-12-27 21:29:36 -08:00 |
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David Harris
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6cf73cdaee
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Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
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2022-12-27 21:24:38 -08:00 |
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David Harris
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c08811357c
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Renamed muldiv to mdu
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2022-12-27 19:57:10 -08:00 |
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Ross Thompson
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66b2fbd836
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-27 15:06:25 -06:00 |
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Ross Thompson
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3f4b3a4159
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Added about moving decompressed config generate.
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2022-12-27 15:04:55 -06:00 |
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David Harris
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dfc0b5d1ad
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Removed MDUE from unnecessary places in fdivsqrt
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2022-12-27 10:42:40 -08:00 |
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David Harris
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4850d058b2
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fdiv typo
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2022-12-27 10:30:42 -08:00 |
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David Harris
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acc9498ae2
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Made SqrtE only true on square root so gating with ~MDUE can be removed)
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2022-12-27 10:27:07 -08:00 |
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David Harris
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e34b8139af
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Check for non-negative W in int sign handling
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2022-12-27 06:35:17 -08:00 |
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Cedar Turek
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f48b7d7ef9
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fpu idiv working on all configs with 1 copy of radix 2!
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2022-12-26 23:18:28 -08:00 |
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Cedar Turek
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0b14aa852d
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fpu passing idiv tests on rv32gc 1 copy of radix 2!
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2022-12-26 21:47:56 -08:00 |
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Cedar Turek
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bebaf08bed
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took out otfc swap. updated postprocessing quotient/remainder logic for int div.
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2022-12-26 21:03:56 -08:00 |
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David Harris
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c326a274ac
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Fixed early termination for square root
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2022-12-26 08:54:57 -08:00 |
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David Harris
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2de66e9eef
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Moved fdivsqrtexpcalc to its own file
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2022-12-26 08:45:43 -08:00 |
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David Harris
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a7204c9012
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Removed unused DivSE from FPU
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2022-12-26 07:29:19 -08:00 |
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David Harris
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fb0b2d4227
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Moved floating-point tests earlier in Wally config
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2022-12-25 22:31:20 -08:00 |
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David Harris
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cd47a7d781
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testcount.pl script to count number of tests in each instruction
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2022-12-25 22:28:58 -08:00 |
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David Harris
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7e77a39d32
|
Restored missing floating point load/store tests
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2022-12-25 22:28:14 -08:00 |
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David Harris
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d627512d2b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-25 20:12:55 -08:00 |
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Ross Thompson
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4f436dc7f0
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Added missing assignment for no branch predictor mode.
|
2022-12-24 17:08:29 -06:00 |
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David Harris
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0cc2b0fcd2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-24 12:24:38 -08:00 |
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Ross Thompson
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ded8f05602
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-24 14:24:25 -06:00 |
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Ross Thompson
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0d6ce1d459
|
Fixed bug with the performance counters not updating.
|
2022-12-24 14:24:17 -06:00 |
|
Ross Thompson
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967d892088
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Updated fpga constraints.
|
2022-12-24 10:21:16 -06:00 |
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David Harris
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10af4e4353
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ALU cleanup
|
2022-12-24 07:18:35 -08:00 |
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Alessandro Maiuolo
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6740624f2d
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added finish message to setup
|
2022-12-23 22:53:39 -08:00 |
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cturek
|
cc6f219bdd
|
Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.
|
2022-12-24 06:46:52 +00:00 |
|
Ross Thompson
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b0d6c9616e
|
Minor optimizations.
|
2022-12-23 20:11:36 -06:00 |
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Ross Thompson
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6e9d1eb180
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-23 19:51:23 -06:00 |
|
Katherine Parry
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4b50ffac91
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reworked negitive sticky bit handeling in fma
|
2022-12-23 17:01:34 -06:00 |
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Ross Thompson
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6f9e21d61b
|
Improved comment.
|
2022-12-23 15:13:15 -06:00 |
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Ross Thompson
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a2de53aeeb
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
|
2022-12-23 15:10:37 -06:00 |
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Ross Thompson
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fe9361de34
|
Removed XEnE, YEnE, and ZEnE from forward logic.
Cleanup comments.
|
2022-12-23 14:27:03 -06:00 |
|
Ross Thompson
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af9afafdae
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Cleanup floating point hazard logic.
|
2022-12-23 14:21:47 -06:00 |
|
Ross Thompson
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b4c7998ded
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DON'T USE. First commit in attempt to move fpustall detection into the decode stage.
|
2022-12-23 12:47:18 -06:00 |
|
Ross Thompson
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f6f66cb79e
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Removed ZForwardEnE and replaced with ZEnE.
Similar for YForwardEnE.
|
2022-12-23 12:27:51 -06:00 |
|
Ross Thompson
|
ca67e5588d
|
Removed unnecessary stall when MatchDE was driven 1 by RdE == 0.
|
2022-12-23 11:45:42 -06:00 |
|
David Harris
|
f038494760
|
Commented out fdiv early termination - broke fsqrt test
|
2022-12-23 00:58:55 -08:00 |
|
David Harris
|
e061bacc9d
|
Fixed early termination on fdivsqrt
|
2022-12-23 00:53:55 -08:00 |
|
David Harris
|
0505f1fd37
|
Moved InstrValidNotFLushed to csr including InstrValidM
|
2022-12-23 00:27:44 -08:00 |
|
David Harris
|
3b1fe78bdc
|
Removed unused StallW from CSRs
|
2022-12-23 00:21:36 -08:00 |
|
David Harris
|
9e21358d75
|
Removed unused signals from FPU
|
2022-12-23 00:18:39 -08:00 |
|
David Harris
|
0a7ed944a5
|
Revert to 98b824
|
2022-12-22 23:58:14 -08:00 |
|
David Harris
|
56312cd0a6
|
Clean up unused FPU signals
|
2022-12-22 23:53:09 -08:00 |
|