Ross Thompson
35ad49502f
Implement FENCE.I as NOP when ZIFENCEI is not supported.
2022-12-20 17:34:11 -06:00
Ross Thompson
0dc09ac22d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 17:11:35 -06:00
Ross Thompson
65cbff9283
Changed long names of vectored pcm signals.
2022-12-20 17:01:20 -06:00
David Harris
f3e9950317
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 14:43:33 -08:00
David Harris
e7702e48b7
FPU remove unused signals
2022-12-20 14:43:30 -08:00
Ross Thompson
6f543d01b7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 16:36:44 -06:00
Ross Thompson
8029b12f2a
Renumbered bits for PCPlusUpper.
2022-12-20 16:33:49 -06:00
David Harris
caef1a6997
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-20 11:23:53 -08:00
David Harris
f0ef5caf32
Memory cleanup
2022-12-20 11:22:26 -08:00
Ross Thompson
c4901450c4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-20 12:58:59 -06:00
Ross Thompson
684d260005
Reorganized IFU PCNextF logic.
2022-12-20 12:58:54 -06:00
David Harris
03c700d91c
Restored rv32d arch test after new push
2022-12-20 10:56:33 -08:00
David Harris
e74d47bcb4
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
David Harris
16f3c25cb7
sram1p1rw cleanup
2022-12-20 02:57:51 -08:00
David Harris
08234cb1c7
Remoed unused bram modules
2022-12-20 02:40:45 -08:00
David Harris
2c46f22be5
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:55 -08:00
David Harris
54e856c4f5
Renamed SRAM2P1R1W to lower case
2022-12-20 02:09:36 -08:00
David Harris
caf457106a
Replaced || and && with single ops
2022-12-20 01:33:35 -08:00
Ross Thompson
dedc08bd42
several options for pcnextf on fence.i
2022-12-19 23:33:12 -06:00
Ross Thompson
2df18cc758
More bp/ifu pcmux cleanup.
2022-12-19 23:16:58 -06:00
Ross Thompson
565585b35a
Moved more muxes inside bp.
2022-12-19 22:51:55 -06:00
Ross Thompson
d8ee0ea59d
Begin cleanup of ifu. partial move of pc muxes inside bp.
2022-12-19 22:46:11 -06:00
David Harris
e4579f3e9b
Removed CSR support from rv32i
2022-12-19 16:15:12 -08:00
David Harris
9fea16fd20
Simplified InstrRawD register
2022-12-19 15:18:42 -08:00
David Harris
a4da3f30e1
Explained hazard causes
2022-12-19 09:41:41 -08:00
David Harris
67763dbeec
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-19 09:09:57 -08:00
David Harris
3172dfd6a9
Properly decode fcvtint to prevent unnecessary stalls
2022-12-19 09:09:48 -08:00
Ross Thompson
159eda85f0
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
5a82898649
Added NumZeroE, AZeroM, and BZeroM
2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
2989782fe6
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
2022-12-18 19:04:36 -08:00
Ross Thompson
6561b8d102
Added files to gitignore.
2022-12-18 18:53:37 -06:00
Ross Thompson
4f56e6ff5d
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
b4229c01ca
Have a basic cache test to fill all ways and sets.
2022-12-18 17:20:30 -06:00
Ross Thompson
376b01fcb8
Attempted to make a cache test.
2022-12-18 17:15:08 -06:00
Ross Thompson
ebdac1a9d0
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
Ross Thompson
e326c9972c
Updated vcu118 piniout.
2022-12-18 14:00:10 -06:00
Ross Thompson
73fd3fe040
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
ade06f3780
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
7d04675073
Cleanup comments.
2022-12-16 17:08:35 -06:00
Ross Thompson
89a30e7e37
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
41c636ecfa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 15:37:03 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
cturek
4b8cbd9fa0
Added integer support for initC
2022-12-16 19:02:11 +00:00
Ross Thompson
bc907f3e2f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 12:52:22 -06:00
Ross Thompson
e425ecac96
Fixed regression-wally to correct remove and mkdir wkdir.
2022-12-16 12:51:21 -06:00
cturek
06c58f310d
Added mux for integer special case, renamed signals to match pipelined stage
2022-12-16 18:43:49 +00:00
