cturek
c72e2e5d49
Added integer inputs and flags to divsqrt
2022-09-29 23:08:27 +00:00
Ross Thompson
f9c4b32bd5
Simplification to EBU.
2022-09-29 18:06:34 -05:00
Ross Thompson
146ff6ff6a
Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
2022-09-29 11:54:03 -05:00
Ross Thompson
638e506d0b
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
87485ed237
Possible fix for ifu/lsu arbiration issue.
2022-09-27 17:24:35 -05:00
Ross Thompson
afc6934249
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
dfe6bdd06d
Found a hidden bug in the cache to bus fsm interlock.
2022-09-26 17:41:30 -05:00
Ross Thompson
f24b0feeed
renamed ahbmulticontroller to ebu.
2022-09-26 14:37:18 -05:00
Ross Thompson
fd47cf05c3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-26 12:49:16 -05:00
Ross Thompson
fd2a8e621a
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
David Harris
b5d2bbe7ca
changed always_ff to always in sram1p1rw to fix testbench complaint
2022-09-25 19:56:40 -07:00
Ross Thompson
dcc00ef4b3
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
6a6686a34b
Removed the write first sram model.
2022-09-22 16:12:08 -05:00
Ross Thompson
8a6ca027c2
The valid and dirty bits match the SRAM implementation now.
2022-09-22 16:09:09 -05:00
Ross Thompson
29087812e1
Solved the sram write first / read first issue. Works correctly with read first now.
2022-09-22 14:16:26 -05:00
Ross Thompson
f74d21e063
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 18:24:06 -05:00
Ross Thompson
cd5b8be78f
Cleaned up the IFU and LSU around dtim and irom address calculation.
2022-09-21 18:23:56 -05:00
David Harris
cfa83fdd98
For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
2022-09-21 13:30:35 -07:00
David Harris
fce927810a
Fixed testbench-fp to support all again
2022-09-21 13:19:48 -07:00
David Harris
f08d5b23d5
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
f83d640068
Updated IROMAdr logic.
2022-09-21 12:42:43 -05:00
Ross Thompson
0294ca0469
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 12:36:52 -05:00
Ross Thompson
cdc80c1f28
Moved other SRAMs to generic/mem.
2022-09-21 12:36:03 -05:00
David Harris
3b0714b059
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 10:35:11 -07:00
David Harris
1c8581dd6d
Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
2022-09-21 10:35:08 -07:00
Ross Thompson
427db1f55f
Renamed brom1p1r to rom1p1r.
...
removed used file bram2p1r1w.sv.
2022-09-21 12:31:20 -05:00
Ross Thompson
234cf7510e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 12:20:12 -05:00
Ross Thompson
91fcca9d17
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
Ross Thompson
d6fa8d51d7
Modified sram1p1rw to support 3 different implementation styles.
...
SRAM, Read first, and Write first.
2022-09-21 11:26:00 -05:00
David Harris
f87e15388a
commented SpecialCase
2022-09-21 05:02:08 -07:00
David Harris
b21e36a788
Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc
2022-09-21 04:55:43 -07:00
David Harris
437fd52bf6
Gated sticky bit in fdiv with SpecialCase
2022-09-20 20:05:00 -07:00
David Harris
cf5c513221
Restored radix 2 to pass regression
2022-09-20 19:30:16 -07:00
David Harris
9c8edb9cb6
renamed u to udigit to avoid conflict with U
2022-09-20 19:29:23 -07:00
cturek
e8f2715a81
Fixed R4 Sqrt overshifting
2022-09-21 00:05:36 +00:00
cturek
49a1259cf9
Fixed fgen4
2022-09-20 20:00:01 +00:00
Ross Thompson
c73fae8a96
Merge branch 'tempMain' into main
2022-09-20 13:57:38 -05:00
Ross Thompson
1c2e47e137
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-20 11:56:53 -05:00
Ross Thompson
b2f4d4aaa7
Added chip enables to sram.
2022-09-20 10:49:14 -05:00
David Harris
33af1f97f7
Define LOGNORMSHIFTSZ
2022-09-20 08:31:57 -07:00
Ross Thompson
7470bf7c7c
Added comment.
2022-09-20 09:49:53 -05:00
Ross Thompson
ea6b687f7c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-20 09:47:16 -05:00
David Harris
811f498f63
renamed q to u for unified digit selection
2022-09-20 04:35:14 -07:00
David Harris
705a2bd97b
Removed D2 and D2b from radix2 stage
2022-09-20 04:20:38 -07:00
David Harris
c77ec2aa9c
Simplified UM initialization
2022-09-20 04:18:12 -07:00
David Harris
956011b40b
fdivsqrtfgen4 comments
2022-09-20 04:13:21 -07:00
David Harris
8d1408a9d6
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
0af8151c2a
Partitioned fdivsqrt into one module per file and added file names to opening comments
2022-09-20 03:57:57 -07:00
David Harris
5b13140078
Simplified fdivsqrtpostproc QmM logic
2022-09-20 03:30:18 -07:00
David Harris
8647de5ee4
make QmM size b+1 indpenedent of radix
2022-09-20 03:25:09 -07:00
David Harris
31c3b62774
clean up divshiftcalc
2022-09-20 03:19:50 -07:00
David Harris
7177745111
clean up divshiftcalc
2022-09-20 03:17:29 -07:00
David Harris
b48bbc4294
clean up divshiftcalc
2022-09-20 03:13:11 -07:00
David Harris
010c88816b
clean up divshiftcalc
2022-09-20 03:08:25 -07:00
David Harris
712f1d8d3a
Cleaning up divshiftcalc LOGNORMSHIFTSZ
2022-09-20 02:35:01 -07:00
Jacob Pease
c797aee62c
Fixed rxfifotimeout restarting for every new character, even when already high.
2022-09-19 18:00:30 -05:00
cturek
85b3e9bfe6
Radix 4 sqrt passing first two tests
2022-09-19 21:26:32 +00:00
Ross Thompson
6a1b909a3f
Fixed up IFU ahb interface names and widths.
2022-09-19 10:54:22 -05:00
David Harris
1e6bd26bb6
Removed EarlyTermShift from fdiv
2022-09-19 08:44:23 -07:00
David Harris
a36747fda0
Finished unified divsqrt otfc and fgen name changes
2022-09-19 08:30:59 -07:00
David Harris
34bd82e4a3
fdivsqrtiter simplification
2022-09-19 01:08:01 -07:00
David Harris
b19c37eb0f
Reduced number of cycles needed for division
2022-09-19 01:02:04 -07:00
David Harris
7826cf0bcb
Cleaned up otfc4
2022-09-19 00:58:20 -07:00
David Harris
6bab8f0e3f
OTFC simplification
2022-09-19 00:51:56 -07:00
David Harris
362056f53d
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
David Harris
32028c437c
fdiv cleanup
2022-09-19 00:32:34 -07:00
David Harris
b7b082482f
Division working again for radix 2 with unified OTFC
2022-09-19 00:30:30 -07:00
David Harris
91194a9c3e
Unified on-the-fly conversion working for radix 2; broke radix-4 division
2022-09-19 00:04:00 -07:00
David Harris
9fb3382ec3
Added 2 bits to C to initialize properly
2022-09-18 22:44:22 -07:00
David Harris
33933dd6b0
Added 2 bits to C to initialize properly
2022-09-18 22:42:35 -07:00
David Harris
24aa410984
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-18 21:27:36 -07:00
David Harris
198a134304
FP testbench
2022-09-18 21:27:21 -07:00
David Harris
1187187a5c
Divide testfloat starts with half-precision tests
2022-09-18 06:46:47 -07:00
Ross Thompson
0fb45cffa1
Removed NonIROM and NonDTIM select signals from IFU and LSU.
2022-09-17 22:01:03 -05:00
Ross Thompson
cc1ba84637
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
David Harris
f65d941561
Reduced number of cycles required for lower-precision sqrt
2022-09-17 09:55:34 -07:00
David Harris
54ad15d595
Starting to adust number of cycles for division/sqrt
2022-09-17 05:58:59 -07:00
cturek
f07d4b3481
Fixed j1 to align with new C reg
2022-09-16 02:15:48 +00:00
Kip Macsai-Goren
a4fc5d3476
Created initial endianness tests
2022-09-16 01:06:26 +00:00
David Harris
a7b5a0419a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-15 12:49:21 -07:00
David Harris
aa1f3ca2be
renamed endianswap
2022-09-15 12:49:18 -07:00
Ross Thompson
4c8ae8b421
Fixed subword read to work with bigendian.
2022-09-15 14:08:04 -05:00
David Harris
877cc63063
FDIVSQRT cleanup
2022-09-15 09:10:57 -07:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
a536829824
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-14 13:59:22 -05:00
cturek
5b35473339
Added shift for radix 4 sqrt
2022-09-14 17:34:24 +00:00
cturek
9757d8ce3e
Moved X-1 to preproc
2022-09-14 17:26:56 +00:00
cturek
0f5b38a6f0
Delete srt
2022-09-14 17:02:42 +00:00
cturek
8378d6b871
removed unnecessary XZero from wsmux
2022-09-14 16:59:52 +00:00
David Harris
4038c4faa9
ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-14 09:42:17 -07:00
Ross Thompson
2ae62c2869
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
40e7d2648f
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
2babf1fd7a
Removed unused signals
2022-09-12 11:35:35 -07:00
David Harris
f45bb25618
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 16:05:58 -07:00
David Harris
1688d544b9
Moved C to shift before rather than after using in an iteration
2022-09-08 16:05:53 -07:00
David Harris
1c3064af08
divsqrt comment cleanup
2022-09-08 15:40:42 -07:00
Ross Thompson
33ef158ff4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 17:15:46 -05:00
David Harris
e0a9b19008
CSA-based completion detection
2022-09-08 14:58:08 -07:00
Ross Thompson
8618045bf2
Optimization. Able to remove hptw address muxes from the E stage.
2022-09-08 15:51:18 -05:00
Ross Thompson
d12ceb46b0
Oups the ahbinterface.sv was accidentally named abhinterface.sv.
2022-09-08 13:21:37 -05:00
