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147 Commits

Author SHA1 Message Date
David Harris
e661b32821 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 13:42:35 -05:00
David Harris
c23afbda3a Moved LoadStall generation to IEU 2021-02-02 13:42:23 -05:00
David Harris
aad1d3d7dd Moved writeback pipeline registers from datapth into DMEM and CSR 2021-02-02 13:02:31 -05:00
Jarred Allen
5090537f3c Fix intermittent errors caused by weird library stuff 2021-02-02 11:20:09 -05:00
Noah Boorstin
8d53e36bbc Busybear: start checking CSRs 
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)

and 3 of the CSRs referenced are skipped because of weird locations for them

oh and this doesn't check their initial state, just their changing. This could be a problem
 2021-02-02 06:06:03 +00:00
David Harris
9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
Jarred Allen
2b75e38239 Fix issues in parallel regression testing 2021-02-01 23:29:03 -05:00
Noah Boorstin
c634b2f81e busybear: start adding CSR checking 
@kaveh is there a less verbose way to do this?
 2021-02-01 22:08:51 -05:00
Brett Mathis
94de3e9fb2 OSU FPU IP initial commit 2021-02-01 19:33:43 -06:00
Noah Boorstin
ff88214730 busybear: change register file checking to only store register changed 
this should make parsedRegs.txt much smaller
 2021-02-02 01:27:43 +00:00
Noah Boorstin
416b3fc96c Add PCW checking 
for now, doesn't check InstrW because it fails on compressed instructions
 2021-02-01 23:57:33 +00:00
David Harris
056b147b13 Renamed DCU to DMEM 2021-02-01 18:52:22 -05:00
Jarred Allen
84801213d6 Parallelize regression-wally.p 2021-02-01 15:40:27 -05:00
Noah Boorstin
a432d607ce busybear: print warning when NOPing out instructions 2021-02-01 19:44:56 +00:00
Noah Boorstin
b7f63c1dc7 busybear: NOP out floating point instructions for now 
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
 2021-01-30 19:52:47 +00:00
Noah Boorstin
4358f086be update busybear testbench to conform to new structure 
aaaaaaaaaaaaaaaaaahhhh so many changes

also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
 2021-01-30 19:19:00 +00:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
fc1fb94217 Working on reading instruction from TIM 2021-01-30 01:57:51 -05:00
David Harris
61fd7c4499 Adding stalls for memory delays 2021-01-30 01:43:49 -05:00
David Harris
9c81278f28 Added HCLK and HRESETn 2021-01-30 00:56:12 -05:00
David Harris
a357f2a0e7 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
73a584b223 Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team 2021-01-29 18:06:36 -05:00
David Harris
e700e404c9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 17:29:01 -05:00
David Harris
9a51bb27c3 Implemented adrdec for uncore 2021-01-29 17:28:53 -05:00
Teo Ene
9eafdbe349 - Removed latch on CSRCReadValM in csrc.sv 
- Changed top level to wallypipelinedhart
 2021-01-29 15:56:51 -06:00
David Harris
8d4f5277d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 15:38:01 -05:00
David Harris
dc2443c55b Moving data memory to uncore 2021-01-29 15:37:51 -05:00
Teo Ene
3d02d6f09f Added AHBW to rv32ic config file as well 2021-01-29 12:29:08 -06:00
Noah Boorstin
194d5b55ab update busybear testbench to conform to new structure 2021-01-29 17:46:50 +00:00
David Harris
a94c09cad8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 01:07:22 -05:00
David Harris
ed3cb83c10 Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
Noah Boorstin
dabb026104 busybear: lie about MISA to match OVP's MISA 2021-01-29 00:58:56 -05:00
Noah Boorstin
8ab5879af5 busybear testbench: test on first 100k instrs 
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
 2021-01-29 00:14:23 -05:00
David Harris
618c6e4813 Renamed modules in privileged unit 2021-01-28 23:21:12 -05:00
David Harris
fd2f854a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 21:40:57 -05:00
David Harris
05b755958f Hint to optimize ifu 2021-01-28 21:40:48 -05:00
Noah Boorstin
619dec1490 busybear: simulate first 10k instructions 
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
 2021-01-28 19:44:58 -05:00
Noah Boorstin
4f84bd3c8f busybear: fix misaligned writing checking 2021-01-28 19:35:09 -05:00
Noah Boorstin
beb93e2508 busybear: add more test instructions 
currently testing first 1k instrs
 2021-01-28 16:41:37 -05:00
Noah Boorstin
287cf4e5a6 oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench 2021-01-28 16:35:12 -05:00
Noah Boorstin
91e9defd0a more of the same fixes 2021-01-28 16:26:15 -05:00
Noah Boorstin
623d9feeab more misaligned read fixing 
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
 2021-01-28 16:14:35 -05:00
David Harris
12c6006f07 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 15:44:14 -05:00
David Harris
fe0876027f Fixed floating signals in clint and ieu 2021-01-28 15:44:05 -05:00
Noah Boorstin
405c9d90b5 busybear testbench: understand bytemask for writes 2021-01-28 15:42:47 -05:00
David Harris
ad5d4793b6 Fixed c.jr instruction improperly writing ra 2021-01-28 15:18:23 -05:00
Noah Boorstin
a4bac85ece busybear: ret is only 1 word 2021-01-28 14:47:40 -05:00
Noah Boorstin
0befdfacec add speculative exception for compressed instructions 2021-01-28 14:40:35 -05:00
Noah Boorstin
27142f0fef testbench now understands lw not aligned to 8 bytes 
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
 2021-01-28 13:33:22 -05:00
Noah Boorstin
a2598b2b30 busybear testbench: check for read data address also 
and check for more end of files better
 2021-01-28 13:16:38 -05:00
Noah Boorstin
f2aea55def update busybear testbench to conform to new structure 2021-01-28 01:21:47 -05:00
Noah Boorstin
206747b8b2 Busybear test now processes first 100 instrs correctly! 
- changed test parser to recognize lw in addition to lw

also, added temporary questa files (wlft*) to .gitignore
 2021-01-28 01:19:27 -05:00
Noah Boorstin
8f6994196a fix memory write address decoding for busybear tests 2021-01-28 01:19:26 -05:00
David Harris
f95d0690ca Created DCU and moved memdp into DCU 2021-01-28 01:03:12 -05:00
David Harris
be1d1886a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-28 00:22:11 -05:00
David Harris
a50b6c2a15 Provided PC + 2 or 4 (PCLink) for JAL 2021-01-28 00:22:05 -05:00
Noah Boorstin
28fabb94ee update busybear testbench to conform to new structure 2021-01-27 23:42:19 -05:00
David Harris
4df461ad77 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 22:49:55 -05:00
David Harris
824014c5c0 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
Noah Boorstin
c9baa70e26 update busybear testbench to conform to new structure 2021-01-27 12:54:09 -05:00
David Harris
616afaba69 Moved privileged unit from datapath to hart 2021-01-27 07:46:52 -05:00
David Harris
e84fbd0a73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 06:40:39 -05:00
David Harris
b88508ca11 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
Noah Boorstin
1195ebb468 show instruction assembly in waveform 2021-01-26 12:34:12 -05:00
Noah Boorstin
6c567aab9a Update busybear tests to conform to new directory structure 2021-01-25 20:37:18 -05:00
Noah Boorstin
e92db93939 Fixed mem write checking 
now passes around 50 instructions!
 2021-01-25 20:07:08 -05:00
Noah Boorstin
358393a1da fix speculation ignoring for PC fetching 2021-01-25 20:07:06 -05:00
David Harris
1d9c741c00 Reset Vector moved to config file 2021-01-25 15:57:36 -05:00
David Harris
fa18052348 Added test configurations 2021-01-25 11:28:43 -05:00
Noah Boorstin
aea1c0cd2e small busybear testbench changes 2021-01-24 20:43:47 -05:00
Noah Boorstin
e7288716f7 Linux testbench works now 
Added parameterized PCSTART to allow compatibility between imperas and busybear tests
Hopefully we are done with the "busybear" branch, please don't use it for future work
 2021-01-24 17:10:00 -05:00
Noah Boorstin
12a8f83025 Merge branch 'busybear' into main 
Merging busybear testbench into main, keeping main edits of wally src
 2021-01-24 16:28:36 -05:00
Noah Boorstin
b08b86f561 sucessfully simulate first 30 instructions 
still need to find a better solution to InstrAccessFault/DataAccessFault though
 2021-01-23 19:01:44 -05:00
Noah Boorstin
a75d7e4555 More linux testbench fixes 
So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(

This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.

Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
 2021-01-23 17:52:05 -05:00
Noah Boorstin
be62987dec Linux test now gets through first 8 instructions! 
fixes the python parser:
  get the value, not function name, of PC
  only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
 2021-01-23 16:46:45 -05:00
David Harris
3905e77e54 Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh 2021-01-23 10:48:12 -05:00
David Harris
170c88bc06 Cleaned up regfile x0 tied to gnd 2021-01-23 10:22:20 -05:00
David Harris
93f8c6f29e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-23 10:19:28 -05:00
David Harris
6b9c6223be Initial checkin of UART 2021-01-23 10:19:09 -05:00
Noah Boorstin
18f6aa716e slightly more info on errors, add instruction decoding 2021-01-22 21:14:45 -05:00
Noah Boorstin
3b16766fde change how testbench reads data 
we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
 2021-01-22 20:27:01 -05:00
Noah Boorstin
4c51a20634 change regfile to not hold state of x0 2021-01-22 15:12:33 -05:00
Noah Boorstin
2c8571aaac change regfile to not hold state of x0 2021-01-22 15:11:55 -05:00
Noah Boorstin
e45f452f25 Start adding register checking 
I'm now realizing we need to simulate loads, or else these will all be wrong
 2021-01-22 15:11:13 -05:00
Noah Boorstin
8104b93900 load instructions from file line by line 2021-01-22 14:11:17 -05:00
Noah Boorstin
40f0b1e328 More testbench setup work 
- Copy bare-bones testbench from E85
   - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
 - Create .gitignore for vsim files
 - Make PC reset a macro, change to 0x1000 to conform to the bootloader

I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo

for now it lives in /mnt/scratch/riscv_testbench/
 2021-01-21 17:55:05 -05:00
Noah Boorstin
795359576b copy testbench to modify for busybear 2021-01-21 16:17:34 -05:00
David Harris
f32c70e866 testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64 2021-01-20 01:04:28 -05:00
David Harris
e3a7fcb5f1 testgen-ADD-SUB initial untested 2021-01-19 22:58:56 -05:00
David Harris
5479342d00 Initial testgen checkin 2021-01-19 13:09:56 -05:00
David Harris
6595c7827f Changed to . notation for instantiation, cleaned up dmem 2021-01-18 20:16:53 -05:00
David Harris
46d02d3818 cleanup 2021-01-18 00:42:40 -05:00
David Harris
18fe5c7c93 Sped up exe2memfile.pl 2021-01-17 18:45:19 -05:00
David Harris
df4d79f8f8 Added exe2memfile.py 2021-01-16 15:09:06 -05:00
David Harris
bfc86182a0 Added GPIO 2021-01-15 00:25:56 -05:00
David Harris
821fb20746 Added GPIO 2021-01-15 00:19:31 -05:00
David Harris
fd01e27a48 Initial Checkin 2021-01-14 23:37:51 -05:00