Noah Boorstin
c8e9edcc43
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
Noah Boorstin
a24270c4ca
busybear: add support for subwords in ram
...
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
2021-02-24 01:51:18 +00:00
Noah Boorstin
00605864fc
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Noah Boorstin
d5e7a8a4cf
busybear: remove unused signals
2021-02-23 19:38:19 +00:00
Noah Boorstin
ceb7df3561
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
kaveh pezeshki
62d9185212
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
Thomas Fleming
21552eaf9d
Create simple TLB
...
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
2021-02-18 18:06:09 -05:00
David Harris
2f5b4c3a25
Resotred part of multiplier for lab 2
2021-02-17 16:14:04 -05:00
David Harris
64536dbc34
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
David Harris
dc758a0c7b
Multiplier tweaks
2021-02-17 16:00:27 -05:00
David Harris
3edf910c18
Started to integrate OSU divider
2021-02-17 15:38:44 -05:00
David Harris
cb0054b524
Multiply instructions working
2021-02-17 15:29:20 -05:00
Noah Boorstin
5835641c6c
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
Noah Boorstin
006f8c6c71
busybear: more small updates
...
not sure what to do about MMU yet, hopefully we'll decide at saturday's meeting
2021-02-16 20:01:00 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
f00728448a
WALLY ALU tests
2021-02-15 10:16:31 -05:00
Domenico Ottolia
75d9091fe8
Add privileged test cases
2021-02-14 17:01:46 -05:00
Teo Ene
e878a8bed2
After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to.
2021-02-14 08:58:33 -06:00
Shreya Sanghai
30bfd7534c
added branch tests
2021-02-12 22:40:08 -05:00
Teo Ene
f25b372c32
Quick commit for Ryan / branch / debugging.
2021-02-12 16:06:02 -06:00
Noah Boorstin
7312da1a99
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
423d3a53e5
add reference output for some tests
2021-02-12 18:33:24 +00:00
Noah Boorstin
97302dd12f
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
bbracker
9231646fb3
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Noah Boorstin
5bf6add635
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
4427780a41
busybear: more updates
...
now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Noah Boorstin
86fcaab831
gdb output combine script updates
...
check that everything is actually the same instruction
update to new 4-file output
this file should be finished for now
2021-02-11 14:59:15 -05:00
Tejus Rao
5158ca4220
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
dfb7333821
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-02-10 20:49:12 -06:00
Teo Ene
8a6de4fb86
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
Teodor-Dumitru Ene
86fcaf0bb1
Added hex code for the pre-compiled, provided, CoreMark binary
2021-02-10 21:22:38 -05:00
Teo Ene
7ca03b2b38
Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions:
...
- RV64I
2021-02-10 20:12:07 -06:00
ethan-falicov
9edc4b6bfe
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
James E. Stine
561ffcf56d
Add ppt and mp4 of wavedrom usage
2021-02-09 13:15:29 -06:00
Jarred Allen
403a0d033c
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74
merge conflict?
2021-02-07 02:34:49 -05:00
Noah Boorstin
01c0f9db63
Busybear: next week of updates
...
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
- parsed first 1M instructions, and now parse from split GDB runs
- now at about 230k instructions, can't progress further for now since atomic instructions
aren't implemented yet
2021-02-07 03:14:48 +00:00
Jarred Allen
48ade25577
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
Jarred Allen
edd758453e
Add test vector set for load instructions
2021-02-06 13:05:59 -05:00
Noah Boorstin
a56ed28160
Update parsing thingy to use split GDB runs
...
huge thanks to kaveh for all his work on this yesterday
2021-02-05 16:46:57 -05:00
James E. Stine
5c017bac1f
Updates to wavedrom
2021-02-05 10:56:29 -06:00
bbracker
691d651fde
JAL testing
2021-02-05 08:08:42 -05:00
Noah Boorstin
14cde0d59c
Change CSR reset and available bits to conform to OVPsim
...
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
2021-02-04 22:03:45 +00:00
James E. Stine
eb468cc40f
sorry ; last update
2021-02-04 15:20:15 -06:00
James E. Stine
0eae86b6e3
Update as overwrite a file :(
2021-02-04 15:11:06 -06:00
James E. Stine
c259cd2e7e
Updates to wavedrom for typos
2021-02-04 14:49:17 -06:00
James E. Stine
a3bd34eb4b
Add some example wavedrom files - more on the way including ppt
2021-02-04 14:41:42 -06:00
