forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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commit
12c6006f07
@ -130,6 +130,6 @@ add wave /testbench_busybear/InstrWName
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run 2640
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run 3850
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#run -all
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##quit
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@ -123,8 +123,12 @@ module testbench_busybear();
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end
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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if (writeDataExpected != WriteDataM) begin
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$display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
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for(int i=0; i<8; i++) begin
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if (ByteMaskM[i]) begin
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if (writeDataExpected[i*8+7 -: 8] != WriteDataM[i*8+7 -: 8]) begin
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$display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
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end
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end
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end
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if (writeAdrExpected != DataAdrM) begin
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$display("%t ps: DataAdrM does not equal writeAdrExpected: %x, %x", $time, DataAdrM, writeAdrExpected);
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