forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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commit
fd2f854a69
@ -54,6 +54,7 @@ add wave -hex /testbench_busybear/MemRWM[0]
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add wave -hex /testbench_busybear/MemRWM[1]
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add wave -hex /testbench_busybear/ByteMaskM
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add wave -hex /testbench_busybear/WriteDataM
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add wave -hex /testbench_busybear/ReadDataM
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add wave -hex /testbench_busybear/DataAdrM
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2]
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@ -130,6 +131,6 @@ add wave /testbench_busybear/InstrWName
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run 3850
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run 129812
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#run -all
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##quit
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@ -170,8 +170,8 @@ module testbench_busybear();
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scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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if (instrs < 10 || (instrs < 100 && instrs % 10 == 0) ||
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(instrs < 1000 && instrs % 50 == 0) || instrs > 205) begin
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if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
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(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0)) begin
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$display("loaded %0d instructions", instrs);
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end
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instrs += 1;
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@ -180,6 +180,8 @@ module testbench_busybear();
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16'bXXXXXXXXX1101111, // JAL
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16'bXXXXXXXXX1100111, // JALR
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16'bXXXXXXXXX1100011, // B
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16'b110XXXXXXXXXXX01, // C.BEQZ
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16'b111XXXXXXXXXXX01, // C.BNEZ
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16'b101XXXXXXXXXXX01: // C.J
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speculative = 1;
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16'b1001000000000010: // C.EBREAK:
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