update busybear testbench to conform to new structure

2021-01-28 01:21:47 -05:00 · 2021-01-28 01:21:47 -05:00 · f2aea55def
commit f2aea55def
parent 206747b8b2
1 changed files with 1 additions and 1 deletions
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@ -21,7 +21,7 @@ module testbench_busybear();
  assign DataAccessFaultM = 0;
   
  // instantiate processor and memories
-  wallypipelinedhart dut(.ALUResultM(DataAdrM), .*);
+  wallypipelinedhart dut(.*);

  // initialize test
  initial