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more misaligned read fixing

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I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
This commit is contained in:
Noah Boorstin 2021-01-28 16:13:10 -05:00
parent 12c6006f07
commit 623d9feeab
1 changed files with 1 additions and 0 deletions
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wally-pipelined/regression/wally-busybear.do
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@ -54,6 +54,7 @@ add wave -hex /testbench_busybear/MemRWM[0]
add wave -hex /testbench_busybear/MemRWM[1]
add wave -hex /testbench_busybear/ByteMaskM
add wave -hex /testbench_busybear/WriteDataM
add wave -hex /testbench_busybear/ReadDataM
add wave -hex /testbench_busybear/DataAdrM
add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1]
add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2]