Noah Boorstin a75d7e4555 More linux testbench fixes ... So I'm super sorry for accidently overwriting the commits this morning Need to be more careful with force pushing :( This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and DataAccessFaultM to zero for now. I feel like this is not a good solution and will cause problems in the future, but for the start it seems to work for now. I'm fair certain we need these to accurately simulate to do linux properly. Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads		2021-01-23 17:52:05 -05:00
..
bin	cleanup	2021-01-18 00:42:40 -05:00
src	More linux testbench fixes	2021-01-23 17:52:05 -05:00
testgen	testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64	2021-01-20 01:04:28 -05:00
lint-wally	Sped up exe2memfile.pl	2021-01-17 18:45:19 -05:00
sim-wally	Initial Checkin	2021-01-14 23:37:51 -05:00
sim-wally-batch	Initial Checkin	2021-01-14 23:37:51 -05:00
wally-busybear.do	More linux testbench fixes	2021-01-23 17:52:05 -05:00
wally-pipelined-batch.do	Initial Checkin	2021-01-14 23:37:51 -05:00
wally-pipelined.do	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
wally.old	Initial Checkin	2021-01-14 23:37:51 -05:00