Ross Thompson
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09dcb56217
|
Signal renames to reflect figures.
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2022-12-14 09:49:15 -06:00 |
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Ross Thompson
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a3ec829b80
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-14 09:34:34 -06:00 |
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Ross Thompson
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6da7849d27
|
Reduced complexity of linebytemask.
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2022-12-14 09:34:29 -06:00 |
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cturek
|
ed59736a4b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-14 15:13:44 +00:00 |
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Ross Thompson
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1ba1bed0b0
|
Broken dont' use.
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2022-12-11 23:24:01 -06:00 |
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Ross Thompson
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0716aedbd5
|
Removed unused flushf.
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2022-12-11 16:28:11 -06:00 |
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Ross Thompson
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115e9e7bb3
|
Renamed CPUBusy to GatedStallF in IFU.
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2022-12-11 15:54:19 -06:00 |
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Ross Thompson
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ffc5bce0b6
|
Renamed CPUBusy in LSU.
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2022-12-11 15:52:51 -06:00 |
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Ross Thompson
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c50a2bd8bf
|
Changed CPUBusy to Stall in ebu modules.
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2022-12-11 15:51:35 -06:00 |
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Ross Thompson
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3ddf509f28
|
Renamed CPUBusy to Stall in cache.
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2022-12-11 15:49:34 -06:00 |
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Ross Thompson
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4aadd87679
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Moved CPUBusy out of HPTW.
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2022-12-11 15:48:00 -06:00 |
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cturek
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f57211bb49
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Ross Thompson
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d15cf5c65c
|
Added comments about why it is not possible to use FlushWay and VictimWay directly.
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2022-12-09 17:07:35 -06:00 |
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Ross Thompson
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1463e9b1d4
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Finished merge of kip and ross's ifu fix.
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2022-12-09 16:52:22 -06:00 |
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Ross Thompson
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6f01ea12e8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-09 16:42:16 -06:00 |
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Ross Thompson
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38adcb5b17
|
Minor simplification of cacheway way selection muxes.
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2022-12-09 16:42:05 -06:00 |
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Kip Macsai-Goren
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f486a763d9
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Addded fix for 32 bit periph test and added test to regression
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2022-12-06 09:56:08 -08:00 |
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Ross Thompson
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033f844d09
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-06 10:38:14 -06:00 |
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Ross Thompson
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9ee2d84c7c
|
Fixed bug Kip found.
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
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2022-12-06 10:37:45 -06:00 |
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Kip Macsai-Goren
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2dfa426e10
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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c6c0ef05db
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commented out periph test from wally32 periph so rv32ic doesn't hang
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2022-12-05 20:23:16 -08:00 |
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Kip Macsai-Goren
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ae32e2a9ee
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added passing tests to regression
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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282d06b45f
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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9806babe9e
|
Renamed SelBusBuffer to SelFetchBuffer.
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2022-12-05 17:51:13 -06:00 |
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Ross Thompson
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0fdbfb87eb
|
Removed commented code.
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2022-12-05 17:21:56 -06:00 |
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Ross Thompson
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bcb927d172
|
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
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2022-12-05 17:19:51 -06:00 |
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Ross Thompson
|
2bcaacb179
|
Cache signal renames.
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2022-12-04 16:09:09 -06:00 |
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Ross Thompson
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b84b709182
|
Optimized way selection logic.
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2022-12-04 12:30:56 -06:00 |
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Ross Thompson
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74d5ccc2b1
|
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
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2022-12-04 01:20:51 -06:00 |
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Ross Thompson
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62e495c739
|
Moved selectedway mux into cacheway. It makes way more sense there.
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2022-12-04 01:15:47 -06:00 |
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Ross Thompson
|
e1ac736d43
|
Rename LineByteMux to FetchbufferbyteSel.
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2022-12-04 01:00:04 -06:00 |
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Ross Thompson
|
128b3d20e7
|
Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Ross Thompson
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de99663b97
|
Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit 70b89e5214.
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2022-12-04 00:01:58 +00:00 |
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cturek
|
70b89e5214
|
Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
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2022-12-02 21:44:29 +00:00 |
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cturek
|
1f32603c30
|
Added flops to preproc
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2022-12-02 20:31:08 +00:00 |
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David Harris
|
9395414df3
|
Renamed FPUStallD to FCvtIntStallD
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2022-12-02 11:55:23 -08:00 |
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David Harris
|
d64cd715f9
|
Renamed DivStartE to IFDivStartE
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2022-12-02 11:30:49 -08:00 |
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David Harris
|
9c1b7e53e4
|
FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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David Harris
|
01028e7088
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-02 04:28:50 -08:00 |
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David Harris
|
4c6003d9e2
|
update test list
|
2022-12-02 04:28:47 -08:00 |
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Ross Thompson
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33e4361de5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 22:36:07 -06:00 |
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David Harris
|
8afc054e74
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 16:27:36 -08:00 |
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David Harris
|
ed39099405
|
reorder tests
|
2022-12-01 16:27:33 -08:00 |
|
Ross Thompson
|
1d9b5badee
|
Properly flush cacheLRU.
|
2022-12-01 17:32:58 -06:00 |
|
David Harris
|
f64c0589fe
|
FPU test list
|
2022-12-01 10:18:36 -08:00 |
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Ross Thompson
|
da92cdccd0
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 11:47:54 -06:00 |
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Ross Thompson
|
cb310bfb1d
|
Removed unused port on cacheway.
|
2022-12-01 11:47:48 -06:00 |
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David Harris
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558f0b655e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 08:15:51 -08:00 |
|
David Harris
|
4e5f62a5c1
|
code cleanup
|
2022-12-01 08:15:48 -08:00 |
|
Ross Thompson
|
b0b16acaf5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 17:19:04 -06:00 |
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David Harris
|
aa26a97b36
|
signal sufixes in integer division
|
2022-11-30 15:15:37 -08:00 |
|
Ross Thompson
|
f9ffcf377b
|
Reverted the IROM/DTIM address range modelsim assignment.
|
2022-11-30 17:13:33 -06:00 |
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Ross Thompson
|
bfd238a4fc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 13:30:37 -06:00 |
|
Ross Thompson
|
813b2963fb
|
More optimization.
|
2022-11-30 11:26:48 -06:00 |
|
Ross Thompson
|
da7b13ba0a
|
Removed reset on dirty cache bits.
|
2022-11-30 11:04:37 -06:00 |
|
Ross Thompson
|
5e5cca6ae1
|
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
|
2022-11-30 11:01:25 -06:00 |
|
Ross Thompson
|
ac3e02692b
|
Preparing to merge dirty and tag srams.
|
2022-11-30 10:40:48 -06:00 |
|
Ross Thompson
|
8692ccbafb
|
Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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cturek
|
e28a6901a9
|
div tests in sim-wally
|
2022-11-30 02:32:04 +00:00 |
|
Ross Thompson
|
e3577781b0
|
Optimization of cacheway.
|
2022-11-29 18:30:47 -06:00 |
|
Ross Thompson
|
1e2180ef98
|
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
|
2022-11-29 17:19:31 -06:00 |
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Ross Thompson
|
5e550fe5e6
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 14:57:38 -06:00 |
|
Ross Thompson
|
9e4166407b
|
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
|
2022-11-29 14:51:09 -06:00 |
|
Ross Thompson
|
179d321683
|
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
|
2022-11-29 14:09:48 -06:00 |
|
Kip Macsai-Goren
|
66fcb2bffe
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 10:43:44 -08:00 |
|
Kip Macsai-Goren
|
26b4147f40
|
added failing satp invalid tests to regression
|
2022-11-29 10:43:38 -08:00 |
|
Ross Thompson
|
ed54959378
|
Renamed signals in the cache.
|
2022-11-29 10:52:40 -06:00 |
|
Ross Thompson
|
4e52755c9f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-22 18:07:32 -06:00 |
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cturek
|
7140642c93
|
Almost done with Int division
|
2022-11-22 22:22:59 +00:00 |
|
cturek
|
3fbccbf119
|
Updated testbench/wave for fdivsqrt new start signals
|
2022-11-22 22:22:26 +00:00 |
|
Ross Thompson
|
1736983557
|
Cleanup cacheLRU.
|
2022-11-22 14:59:01 -06:00 |
|
Ross Thompson
|
2ae7b555be
|
File name change for cachereplacement policy to cacheLRU
|
2022-11-20 22:35:02 -06:00 |
|
Ross Thompson
|
84679c0062
|
Signal name changes for LRU.
|
2022-11-20 22:31:36 -06:00 |
|
Ross Thompson
|
736a30afac
|
Missing a file. Last commit will fail.
|
2022-11-17 17:45:41 -06:00 |
|
Ross Thompson
|
a1f39a8186
|
Finally have the correct replacement policy implementation.
|
2022-11-17 17:36:37 -06:00 |
|
Ross Thompson
|
ac0f6ddb7b
|
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
|
2022-11-16 15:38:37 -06:00 |
|
Ross Thompson
|
9b2236b2a0
|
Progress on the cache replacement policy implementation.
|
2022-11-16 15:35:34 -06:00 |
|
Ross Thompson
|
cf964e30fb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-16 12:42:29 -06:00 |
|
Ross Thompson
|
5f7b0b8a9b
|
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
|
2022-11-16 12:36:58 -06:00 |
|
David Harris
|
bc3b783543
|
comment cleanup
|
2022-11-16 10:23:20 -08:00 |
|
David Harris
|
ddba68605e
|
Renamed DivBusy to FDivBusyE in FPU
|
2022-11-16 10:13:27 -08:00 |
|
David Harris
|
e008d663f4
|
Moved DivStartE to fdivsqrtfsm
|
2022-11-16 10:00:07 -08:00 |
|
Ross Thompson
|
900a326a23
|
Created improved cache replacement policy implementation. This version is generic and works for any number of ways. Not fully tested and is currently commented out.
|
2022-11-16 11:15:34 -06:00 |
|
cturek
|
6fe35ee0e3
|
Attempt to fix FPGA synth errors
|
2022-11-15 20:34:28 +00:00 |
|
cturek
|
1c49d4a1c2
|
Fixed lint errors in postprocessing
|
2022-11-15 20:31:23 +00:00 |
|
Ross Thompson
|
ec6517fadd
|
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
|
2022-11-14 16:02:20 -06:00 |
|
Ross Thompson
|
f03d5d3ac8
|
Renamed Flush to FlushStage in the cache.
|
2022-11-14 14:11:05 -06:00 |
|
Ross Thompson
|
1bf838fa6b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-14 13:48:56 -06:00 |
|
David Harris
|
895ee3d773
|
Removed comment about nonexistent possible bug
|
2022-11-14 09:56:33 -08:00 |
|
David Harris
|
cae3e00751
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-14 09:52:24 -08:00 |
|
David Harris
|
79d416537a
|
Removed comment about nonexistent possible bug
|
2022-11-14 09:52:21 -08:00 |
|
Ross Thompson
|
1a00e7bbee
|
Changed names of cache signals.
|
2022-11-13 21:36:12 -06:00 |
|
Ross Thompson
|
5800dfde60
|
Updated wave file.
|
2022-11-13 21:34:45 -06:00 |
|
cturek
|
0b2c8b9d46
|
Added majority of combinational logic
|
2022-11-14 00:06:38 +00:00 |
|
cturek
|
74f58b5d89
|
Added Quotient/Remainder calcs to normal termination
|
2022-11-13 23:44:34 +00:00 |
|
cturek
|
b3bfdbad18
|
Added flops for n and m, added B=0 signal
|
2022-11-13 23:02:43 +00:00 |
|
cturek
|
9c70ab917c
|
Added A<B signal to fdivsqrt, started postprocessing merge
|
2022-11-13 22:40:26 +00:00 |
|
Ross Thompson
|
a27b81ef90
|
Changed IMWriteDataM to IHWriteDataM.
|
2022-11-13 12:27:48 -06:00 |
|
Ross Thompson
|
3ac6514856
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
|
2022-11-13 12:25:22 -06:00 |
|
David Harris
|
0ce3cc393a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-13 04:23:26 -08:00 |
|