Ross Thompson
|
6581490f9c
|
Modified regression tests to add some ahb configurations.
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2022-09-07 12:03:58 -05:00 |
|
DTowersM
|
dedfadbb14
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-31 00:18:04 +00:00 |
|
DTowersM
|
f9cbc9cf8e
|
fixed qrduino keyerror in embench test
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2022-08-31 00:17:58 +00:00 |
|
David Harris
|
5956fbdd62
|
Fixed checking termination in testfloat testbench
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2022-08-30 10:55:21 -07:00 |
|
David Harris
|
b4cb9a678a
|
renamed srt to fdivsqrt
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2022-08-29 04:04:05 -07:00 |
|
David Harris
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921a49921b
|
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
|
David Harris
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6409548c8b
|
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
|
David Harris
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906f6f2990
|
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
|
Ross Thompson
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109bcd470e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-25 16:01:02 -05:00 |
|
David Harris
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6222e15946
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Extended HADDR to PA_BITS
|
2022-08-25 13:11:36 -07:00 |
|
Ross Thompson
|
32f86b1b6b
|
Still not working with rv32ic.
|
2022-08-25 15:03:54 -05:00 |
|
Ross Thompson
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4ad7ccc7f7
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Possible fixes for earily messup of rv32ic and rv64ic configs.
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2022-08-25 14:42:08 -05:00 |
|
Ross Thompson
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bd9401179d
|
BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
|
Ross Thompson
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5cc4f1f1cd
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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David Harris
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fe3147806d
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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David Harris
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b3a13a01f8
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
|
Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c636387613
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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07b2858890
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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9e3d13ca52
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
|
David Harris
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7c91ed38a3
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
|
David Harris
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b795cf4731
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Updated testbench assertions.
|
2022-08-23 07:23:24 -07:00 |
|
Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
|
Ross Thompson
|
dad6770fc3
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Updated fpga testbench.
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2022-08-21 14:07:26 -05:00 |
|
Katherine Parry
|
0f077012c3
|
sqrt tests in regression uncommented and pass
|
2022-08-07 23:38:10 +00:00 |
|
Katherine Parry
|
8eeca3319c
|
radix-2 1 copy passes testfloat
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2022-08-06 22:54:05 +00:00 |
|
David Harris
|
8b8f045491
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
|
David Harris
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6ee8036ae7
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
e3b970d3ff
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Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
|
David Harris
|
da275e3c26
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
|
David Harris
|
ae4ea00ff0
|
fixed testbench merge comflict
|
2022-07-26 06:21:46 -07:00 |
|
David Harris
|
449c80b5f7
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
094aacdf6f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-25 23:29:08 +00:00 |
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David Harris
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ccf8ccfa24
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Added rv32f tests to RV64gc
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2022-07-25 23:29:05 +00:00 |
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David Harris
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539174f6f6
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Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
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2022-07-25 16:23:10 -07:00 |
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Ross Thompson
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70032bf8f4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-23 08:41:59 -05:00 |
|
Katherine Parry
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ee7932c804
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divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Daniel Torres
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d95b266d49
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
|
slmnemo
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44c30ec082
|
fixed error in tests.vh
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2022-07-22 14:55:55 -07:00 |
|
slmnemo
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170601af0b
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Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
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Daniel Torres
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fbe3a1af12
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
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261b9aa5a1
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commented out embench test that should be commented out
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2022-07-22 13:52:13 -07:00 |
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slmnemo
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0d98ff74b4
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Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
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Daniel Torres
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5d7171f6f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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526f70e772
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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slmnemo
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49565f944c
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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Daniel Torres
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bd918d37ba
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added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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Daniel Torres
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a17361870f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
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6e9b4f4075
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Daniel Torres
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d33d0d22bd
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commented out embench 2.0 tests
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2022-07-19 13:36:18 -07:00 |
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Katherine Parry
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4c2afbbc4f
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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e599f82b29
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Katherine Parry
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921debf930
|
removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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5bb1478859
|
renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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Ross Thompson
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a88543275f
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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3670c47141
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
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2022-07-17 16:20:04 -05:00 |
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Katherine Parry
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e251022269
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
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Katherine Parry
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b069cfbec2
|
fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
|
Katherine Parry
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77ea4e47cb
|
removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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Katherine Parry
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e05b2a07d2
|
removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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Katherine Parry
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2ada8a8bc1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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7815b81716
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-11 18:30:29 -07:00 |
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Katherine Parry
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b728e5054d
|
variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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DTowersM
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191c7a2ee3
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added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
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2022-07-11 21:13:09 +00:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Katherine Parry
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3476579e02
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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9ef45f36fd
|
renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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David Harris
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d10ad0e883
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Removed testbench code that ignores mismatch on zero signatures
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2022-07-08 09:17:31 +00:00 |
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DTowersM
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5a68ff9afb
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-07 23:11:35 +00:00 |
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DTowersM
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d55833e4f3
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new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
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2022-07-07 23:11:02 +00:00 |
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Katherine Parry
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41c16be012
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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David Harris
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2f342c430e
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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0b40f38f02
|
added load and store test
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2022-07-07 21:48:51 +00:00 |
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DTowersM
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47a990d9f1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-06 23:44:27 +00:00 |
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DTowersM
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1e8ccf3449
|
added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
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2022-07-06 23:43:57 +00:00 |
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David Harris
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dab87811e9
|
Removed sig4 spurious message from testbench
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2022-07-05 03:27:14 +00:00 |
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Katherine Parry
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010a05f583
|
added missing files
|
2022-07-03 21:40:47 -07:00 |
|
Katherine Parry
|
1b4584e825
|
Renaming signals to match chapter
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2022-07-03 12:26:22 -07:00 |
|
Daniel Torres
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a384a6465b
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
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Daniel Torres
|
50b9b4557c
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
slmnemo
|
448c9fdbb9
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
|
Katherine Parry
|
f25bb4a384
|
radix-4 early termination working for special cases - not working completely
|
2022-06-27 20:43:55 +00:00 |
|
Katherine Parry
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06f7f9b147
|
fixed commented out error and removed killprod from result selection
|
2022-06-25 01:42:23 +00:00 |
|
Katherine Parry
|
d058ec6329
|
added denormal input handeling - radix 4
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2022-06-24 19:41:40 +00:00 |
|
Katherine Parry
|
b54d84195f
|
added radix-4 0/d handling
|
2022-06-23 22:36:19 +00:00 |
|
Katherine Parry
|
5133b08161
|
generate qsel4 in verilog
|
2022-06-23 21:38:04 +00:00 |
|
Katherine Parry
|
49067792dc
|
fixt lint error
|
2022-06-23 16:11:50 +00:00 |
|
Katherine Parry
|
4a6dee5926
|
Testfloat running division - not passing
|
2022-06-23 00:07:34 +00:00 |
|
David Harris
|
8537b883d1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-21 22:45:28 +00:00 |
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slmnemo
|
2b2760f5bd
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
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slmnemo
|
2b2ddbcc5e
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
254ebf478e
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
Daniel Torres
|
d077199608
|
embench and testbench now support running both O2 and Os build variations without overwriting one another
|
2022-06-17 21:15:42 -07:00 |
|
Daniel Torres
|
1ef5ed8005
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
dcdd3702c3
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
3a5c02b44a
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
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David Harris
|
ecd733942a
|
Removed testbench.sv.bak
|
2022-06-14 22:04:38 +00:00 |
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DTowersM
|
919c1818a8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
|
1f4d56ba32
|
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
|
2022-06-13 23:23:57 +00:00 |
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Katherine Parry
|
31fd8772cf
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
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DTowersM
|
4bbe5eeecd
|
simplified coremark
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2022-06-10 19:15:17 +00:00 |
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slmnemo
|
284e0395a0
|
Merge branch 'main' into cacheburstmode
|
2022-06-08 02:21:33 +00:00 |
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DTowersM
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a190342b8a
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 23:58:58 +00:00 |
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DTowersM
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02a424d65b
|
modified testbench.sv- now works with coremark
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2022-06-07 23:58:50 +00:00 |
|
DTowersM
|
e324db71b4
|
cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000
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2022-06-07 23:27:54 +00:00 |
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DTowersM
|
df330961b8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-07 06:03:19 +00:00 |
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DTowersM
|
590cf243bb
|
added support for 64 bit rv tests
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2022-06-07 06:02:23 +00:00 |
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Katherine Parry
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cfcaddf8aa
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-06 16:06:54 +00:00 |
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Katherine Parry
|
8fa0fc4229
|
fma synth warnings and errors removed
|
2022-06-06 16:06:04 +00:00 |
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slmnemo
|
3fe78c9084
|
Fixed recurrent issue with testbench where it would never stop
|
2022-06-03 18:56:24 -07:00 |
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DTowersM
|
caaf56cbf7
|
testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh
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2022-06-03 22:07:14 +00:00 |
|
Katherine Parry
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6b39b8c702
|
fixed compilation errors
|
2022-06-03 15:34:17 +00:00 |
|
Katherine Parry
|
8420b1e87c
|
removed some debuging code accedentally pushed
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2022-06-02 22:45:19 +00:00 |
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slmnemo
|
c8515001a2
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-02 12:54:08 -07:00 |
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Katherine Parry
|
9a09ee3a35
|
fpu paramaterized - except fdivsqrt
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2022-06-02 19:50:28 +00:00 |
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slmnemo
|
88454aa2ab
|
Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do"
This reverts commit 89c7438424.
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2022-06-02 12:45:21 -07:00 |
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slmnemo
|
ad9e85beb9
|
Revert "Fixed buildroot by adding a second ."
This reverts commit 8b27c1884e.
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2022-06-02 12:43:59 -07:00 |
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David Harris
|
197b588193
|
Cleaned up test cases in testbench
|
2022-06-02 08:44:28 -07:00 |
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slmnemo
|
c16c5beef5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-02 02:52:03 +00:00 |
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slmnemo
|
65961223f8
|
Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files
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2022-06-02 02:51:51 +00:00 |
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DTowersM
|
215f69a2ab
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-01 21:00:51 +00:00 |
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DTowersM
|
d28b4cf602
|
added support for embench post processing to testbench.sv
|
2022-06-01 21:00:44 +00:00 |
|
Katherine Parry
|
dd19e55b8f
|
unpacker optimizations
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2022-06-01 16:52:21 +00:00 |
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DTowersM
|
8903af3764
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-05-31 20:13:41 +00:00 |
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DTowersM
|
525f6a6069
|
added testbench.sv support for embench tests, test output still WIP
|
2022-05-31 20:13:32 +00:00 |
|
DTowersM
|
95df88ae70
|
added embench tests to tests.vh
|
2022-05-31 20:08:04 +00:00 |
|
Katherine Parry
|
950a17bef5
|
fixed lint error
|
2022-05-28 10:20:13 -07:00 |
|
slmnemo
|
f18989e801
|
Revert Commit 6c61840045
|
2022-05-28 03:35:17 -07:00 |
|
slmnemo
|
6c61840045
|
Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do
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2022-05-28 03:14:49 -07:00 |
|
Katherine Parry
|
a0ff98042c
|
unpacker adds 1 to denorm expoents
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2022-05-27 14:37:10 -07:00 |
|
Katherine Parry
|
95b506c5e0
|
some optimizations in unpacker
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2022-05-27 11:36:04 -07:00 |
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Katherine Parry
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3c04f1bdec
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-26 20:48:30 +00:00 |
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Katherine Parry
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9d281b2604
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fcvt.sv paramaterized
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2022-05-26 20:48:22 +00:00 |
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DTowersM
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7ffef6ccfa
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fixed indent spacing (cosmetic change)
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2022-05-26 19:04:21 +00:00 |
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slmnemo
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d1421b88ad
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Added line to testbench to prevent annoying burst sizes
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2022-05-25 17:29:45 -07:00 |
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DTowersM
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de60b15cfe
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-26 00:12:46 +00:00 |
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slmnemo
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b5476204da
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see commit 9042cc3c
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2022-05-25 17:10:59 -07:00 |
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DTowersM
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a1cda79cd5
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Merge branch 'embench' into main
embench contained the working makefiles for embench and is being merged into main as it working and done
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2022-05-26 00:10:50 +00:00 |
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DTowersM
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3f7eddbc89
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working makefile for embench and removed testbench-f64
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2022-05-26 00:08:18 +00:00 |
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slmnemo
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4e5505f301
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added logic to prevent cache line length from exceeding the max size of a burst.
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2022-05-25 17:03:15 -07:00 |
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Katherine Parry
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f35450207f
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single and double conversions pass all tests
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2022-05-25 23:02:02 +00:00 |
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slmnemo
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e3a7e3e2f3
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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Katherine Parry
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5d34db85b2
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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slmnemo
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79c28d34dc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-19 17:51:45 -07:00 |
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slmnemo
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8b27c1884e
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Fixed buildroot by adding a second .
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2022-05-19 17:49:32 -07:00 |
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