Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
David Harris
f45fe48158
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
David Harris
64f33161bc
Added files to repo
2021-12-04 20:25:33 -08:00
Skylar Litz
546f7fb4c2
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
500e6ff430
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
b03ca464f1
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
9ccc8e7f3a
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
kwan
5164129172
.* resolved in ifu.sv
2021-12-02 10:32:35 -08:00
kwan
05a838aee2
.* in ifu/ifu.sv eliminated
2021-12-02 09:45:55 -08:00
David Harris
42780ba40b
Added coremark scripts to regression directory
2021-12-01 09:08:06 -08:00
David Harris
a146d7a618
testing push
2021-11-30 11:20:09 -08:00
Ross Thompson
97c73f10ff
Fixed uart for FPGA config after merge. This still needs some work.
2021-11-29 16:07:54 -06:00
Ross Thompson
a871118116
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
fed0bb08d6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
Noah Limpert
09d3322a26
updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
2021-11-24 23:22:04 -08:00
Noah Limpert
93b626ce2a
replaced .* instation of priv module on wallypiplinedhart
2021-11-24 22:58:59 -08:00
Noah Limpert
f36cc7a2a3
Made abhlite instation on wallypipehart more clear, updated spacing for consistency
2021-11-24 22:48:01 -08:00
Noah Limpert
5b7c969170
updated module instation of LSU on wallypiplinedhard
2021-11-24 22:09:39 -08:00
bbracker
23194c0308
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
Ross Thompson
1183aed049
Missed another change to uart.
2021-11-23 10:20:47 -06:00
Ross Thompson
3fc370654d
Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
2021-11-23 10:00:32 -06:00
Ross Thompson
f12e7e1b68
Added QEMU hack for initial LCR value in uart.
2021-11-22 15:23:19 -06:00
Ross Thompson
f05a66acd1
Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
2021-11-22 15:20:54 -06:00
Ross Thompson
d5cf6da6eb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-22 11:30:14 -06:00
bbracker
cffb72042a
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Ross Thompson
e955b17500
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:44:45 -06:00
Ross Thompson
055a5bd202
Removed unneeded check for icache ways.
2021-11-20 22:44:37 -06:00
Ross Thompson
9d3261ed49
Reversed bit order in uart.
2021-11-20 22:43:05 -06:00
Ross Thompson
88b4e0946f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:37:15 -06:00
Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
bbracker
4e96d0f1db
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
e5d3416258
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
bbracker
713aa7faac
automatic bug finder script
2021-11-19 20:25:00 -08:00
bbracker
c07caf4fe8
increase buildroot progress expecttions; increase timeout to 20 hours
2021-11-19 12:52:11 -08:00
David Harris
82cfebfb83
Coremark Cleanup, trying compile from addins
2021-11-19 06:09:04 -08:00
David Harris
a801e0dbec
Moved exe2memfile.pl
2021-11-18 20:32:13 -08:00
David Harris
690410721d
Cleaning up CoreMark benchmark
2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532
vert "Simplifying riscv-coremark"
...
This reverts commit ce8232e396
2021-11-18 18:40:13 -08:00
David Harris
ce8232e396
Simplifying riscv-coremark
2021-11-18 17:15:40 -08:00
David Harris
b73e6354e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-18 16:14:42 -08:00
David Harris
402b473dbb
CoreMark testing
2021-11-18 16:14:25 -08:00
slmnemo
0bf1836a3a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
slmnemo
5c28553ca1
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
2021-11-17 14:08:08 -08:00
slmnemo
df6c54a664
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:38:51 -08:00
slmnemo
bf8cef78bc
removed .* from muldiv.sv (REAL)
2021-11-17 13:37:50 -08:00
David Harris
0a281a06e0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:28:33 -08:00
Noah Limpert
b63c0f35d1
ieu variable naming changed for clarity
2021-11-17 13:24:28 -08:00
slmnemo
c5c886ddc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:23:20 -08:00
slmnemo
40efffc70b
Removed .*s from muldiv.sv
2021-11-17 13:23:12 -08:00
Noah Limpert
bbd17e730b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:04:33 -08:00
Noah Limpert
70a84b56c8
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kevin Kim
6437c04074
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 12:18:25 -08:00
Kevin Kim
38437c664e
root level makefile added
2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
Ross Thompson
23e78c4842
Fixed uart by reversing the bit order on transmit.
...
Set prescale to 0.
2021-11-17 10:32:41 -06:00
Skylar Litz
6fde97b16c
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
David Harris
c610be25a7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
bbracker
2203590f9f
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Ross Thompson
1c9670d739
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Skylar Litz
3dd83b3113
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
David Harris
570f24a9e4
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
Kevin Kim
7cb8b76ef6
Makefile added in regression directory:
...
-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
f6a555009b
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
c92d41a597
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
bc6332a780
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
17e776f853
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
Kevin
11efaa2669
changed code aligner to run recursively on a root directory
...
-only runs the aligner on .sv files
-runs recursively on sub-directories
2021-11-03 10:49:34 -07:00
bbracker
0c7681b942
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
bbracker
526aff54a8
linux testgen refactor
2021-11-01 14:09:49 -07:00
David Harris
d7f0abca5a
Add3d wally32i test
2021-11-01 13:17:49 -07:00
David Harris
dda035891a
PIPELINE test running
2021-11-01 12:44:35 -07:00
David Harris
60573b92b2
Adding custom Wally test infrastructure
2021-11-01 08:48:46 -07:00
bbracker
fe2cda493c
fix buildroot graphical sim
2021-10-31 18:33:43 -07:00
David Harris
360930fe8b
Fixed exe2memfile parsing of weird line in arch64d test
2021-10-30 07:26:18 -07:00
David Harris
bd1a4769ab
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-29 22:32:08 -07:00
David Harris
247f247ad3
tesgen cleanup, added riscv-arch-test D tests
2021-10-29 22:31:48 -07:00
David Harris
14b9b8126e
rearranging testgen
2021-10-29 22:28:37 -07:00
Ross Thompson
9c875d38a9
Fixed the 4 way set associative pseudo LRU replacement policy.
2021-10-29 12:46:02 -05:00
Ross Thompson
41dbb59e24
Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
2021-10-29 11:03:37 -05:00
Ross Thompson
35fcadbe7f
Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
2021-10-28 11:07:18 -05:00
bbracker
7158bf1d4f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-27 14:40:31 -07:00
bbracker
ab711c498d
checkpoint generator off-by-one error fix
2021-10-27 14:10:29 -07:00
Noah Limpert
27251a9935
Have replaced .* with signal names in ifu
2021-10-27 13:45:37 -07:00
koooo142857
33f5de0f5c
aligned all files in ifu folder
2021-10-27 12:43:55 -07:00
David Harris
7df4b0c8e7
commented out some failing FPU tests
2021-10-27 11:27:34 -07:00
David Harris
582c2bf37b
Fixed FResultSelM to select proper flags
2021-10-27 11:02:42 -07:00
David Harris
589bee5875
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-27 10:37:46 -07:00
David Harris
5783e47e1a
Changes for floating point sims
2021-10-27 10:37:35 -07:00
Ross Thompson
7627e177df
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-27 09:59:55 -05:00
Ross Thompson
c4170ece27
Replaced async reset flip flops with sync reset flip flops in cache and bpread.
2021-10-27 09:57:11 -05:00
Ross Thompson
400670cb06
Linux now boots fpga.
2021-10-26 16:49:16 -05:00
bbracker
c457fc6e27
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-26 12:43:48 -07:00
bbracker
1591a40f68
bugfix argument passing to GDB script; remove outdated GDB script
2021-10-26 12:43:42 -07:00
David Harris
b7b6d6f23f
removed unused signal from wave.do
2021-10-26 09:02:22 -07:00
David Harris
90cf37b881
commented out nonworking tests
2021-10-26 08:56:49 -07:00
David Harris
67adc1d7d5
removed referenc outputs
2021-10-26 08:51:49 -07:00
David Harris
426a43f77b
Forgot to save cacheway merge
2021-10-26 08:38:13 -07:00
David Harris
c0145c0a35
merging changes
2021-10-26 08:34:36 -07:00
David Harris
8287a1ef3e
Synchronous reset in non-flop blocks
2021-10-26 08:30:35 -07:00
Ross Thompson
c43b19120f
Fixed another critical path in the caches.
2021-10-25 22:05:11 -05:00
Ross Thompson
1228dbbebc
Fixed the timing issue in the cache replacement polcy.
2021-10-25 18:00:23 -05:00
Ross Thompson
576383c74b
Fixed bug with the changes to sram1rw.
2021-10-25 16:11:41 -05:00
Ross Thompson
f0beb4357a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-25 15:36:21 -05:00
Ross Thompson
5fd3f7f2c7
Possible fix for critical path timing in caches.
2021-10-25 15:33:33 -05:00
bbracker
66e53929ce
adapt testbench linux to use reset_ext
2021-10-25 13:26:44 -07:00
bbracker
787b54dffc
copy / link to checkpoint 8500000 dir
2021-10-25 13:24:02 -07:00
Ross Thompson
81054d9168
Fixed issue with dtim (fpga) external abhlite select not triggering.
...
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
2021-10-25 14:51:54 -05:00
bbracker
39efadf2cf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-25 12:25:37 -07:00
bbracker
8c4e6baf48
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
2021-10-25 12:25:32 -07:00
Ross Thompson
32f0b97cd3
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
David Harris
fbee4963da
Converted flops to synchronous reset now that reset signal is synchronized
2021-10-25 11:49:20 -07:00
David Harris
2bf51362e2
Added synchronizer to reset
2021-10-25 10:05:41 -07:00
bbracker
9b98a499d7
some linux testbench cleanup
2021-10-25 10:04:30 -07:00
Ross Thompson
76bba541a7
Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.
2021-10-24 21:21:49 -05:00
bbracker
9fdfc750eb
checkpoint initialization bugfix
2021-10-24 18:39:51 -07:00
bbracker
13763b002a
switch linux graphical sim over to Ross's waves
2021-10-24 18:39:23 -07:00
bbracker
fef09e9a5b
remove unused scripts
2021-10-24 15:19:03 -07:00
bbracker
09959617c6
update debugger script to new style
2021-10-24 15:18:44 -07:00
bbracker
cc484569cd
fix typo
2021-10-24 15:05:00 -07:00
bbracker
046a78a8fc
manually resolved git merge conflicts in testbench linux after checkpointing
2021-10-24 15:02:19 -07:00
bbracker
3531a934c9
checkpoint generator bugfix
2021-10-24 14:46:56 -07:00
Ross Thompson
8a51fe76c1
Partial cleanup of unused signals in caches and bpred.
2021-10-24 15:04:20 -05:00
bbracker
c0a7b12f94
or actually needed to reduce expectations of buildroot
2021-10-24 06:59:34 -07:00
bbracker
d3969bb1ba
increase regression's expectations of buildroot
2021-10-24 06:50:22 -07:00
bbracker
36b39358c6
add checkpointing to linux testbench
2021-10-24 06:47:35 -07:00
bbracker
d445095f1b
revamp linux testvector generation for refactoring checkpoint generation
2021-10-24 06:14:11 -07:00
bbracker
e0b6566cbd
buildroot do scripts now compile flops
2021-10-23 23:14:59 -07:00
bbracker
26eead1c77
add W stage signals to linux testbench
2021-10-23 14:00:53 -07:00
bbracker
de6a52f6eb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-23 13:17:37 -07:00
bbracker
3c0b0987d2
add option for regression to do a partial execution of buildroot
2021-10-23 13:17:30 -07:00
David Harris
200eb453fb
wrapping up lint cleanup; many unused signals removed
2021-10-23 12:15:14 -07:00
David Harris
c9e9cd4a60
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
62a23fe878
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
61fdb3d902
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
8d9efcbafb
IEU cleanup
2021-10-23 11:13:28 -07:00
David Harris
4bf823e063
lint cleanup
2021-10-23 11:03:28 -07:00
David Harris
d570df864f
IEU lint cleanup
2021-10-23 10:51:53 -07:00
David Harris
8e516e6391
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
33358d101e
Lint cleanup: ahblite, ifu, hart
2021-10-23 10:12:33 -07:00
David Harris
d24bece3a8
Lint cleanup
2021-10-23 09:58:52 -07:00
David Harris
2e796e3da2
lint cleanup: FPU and privileged
2021-10-23 09:41:24 -07:00
David Harris
c316bff15a
subword read and csrc lint cleanup
2021-10-23 09:29:15 -07:00
David Harris
28d8f6d5cf
FMA and CSRC lint cleanup
2021-10-23 09:20:24 -07:00
David Harris
11b0607e63
Lint cleanup
2021-10-23 09:06:21 -07:00
David Harris
ac1b1bfbb6
update scripts for handling src/*/* subdirectories
2021-10-23 08:54:29 -07:00
David Harris
0dabb6ebd4
lint cleaning and moved files into subdirectories
2021-10-23 08:53:32 -07:00
