forked from Github_Repos/cvw
CoreMark testing
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David Harris
parent
0a281a06e0
commit
402b473dbb
@ -195,8 +195,11 @@ void stop_time(void) {
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*/
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CORE_TICKS get_time(void) {
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CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
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//ee_printf(" Elapsed MTIME: %u\n", elapsed);
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//ee_printf(" Elapsed MINSTRET: %lu\n", minstretDiff());
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unsigned long instructions = minstretDiff();
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double CPI = elapsed / instructions;
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ee_printf(" Elapsed MTIME: %u\n", elapsed);
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ee_printf(" Elapsed MINSTRET: %lu\n", instructions);
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ee_printf(" CPI: %lf", CPI);
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return elapsed;
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}
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/* Function: time_in_secs
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@ -1,3 +1,3 @@
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vsim -c <<!
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do wally-pipelined-batch.do rv64g arch64d
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do wally-pipelined-batch.do rv32g arch32f
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!
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@ -1,118 +0,0 @@
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# wally-coremark.do
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# Use this wally-coremark.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally-coremark.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally-coremark.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# default to config/coremark, but allow this to be overridden at the command line. For example:
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vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench -o workopt
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vsim workopt
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mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM
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view wave
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-- display input and output signals as hexidecimal values
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# Diplays All Signals recursively
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add wave /testbench/clk
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add wave /testbench/reset
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add wave -divider
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#add wave /testbench/dut/hart/ebu/IReadF
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#add wave /testbench/dut/hart/DataStall
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#add wave /testbench/dut/hart/InstrStall
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#add wave /testbench/dut/hart/StallF
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#add wave /testbench/dut/hart/StallD
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#add wave /testbench/dut/hart/FlushD
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#add wave /testbench/dut/hart/FlushE
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#add wave /testbench/dut/hart/FlushM
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#add wave /testbench/dut/hart/FlushW
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add wave -divider Fetch
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add wave -hex /testbench/dut/hart/ifu/PCF
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add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave /testbench/InstrFName
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add wave -divider Decode
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add wave -hex /testbench/dut/hart/ifu/PCD
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add wave -hex /testbench/dut/hart/ifu/InstrD
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add wave /testbench/InstrDName
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add wave -divider Execute
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add wave -hex /testbench/dut/hart/ifu/PCE
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add wave -hex /testbench/dut/hart/ifu/InstrE
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add wave /testbench/InstrEName
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add wave -divider Memory
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add wave -hex /testbench/dut/hart/ifu/PCM
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add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave /testbench/InstrMName
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add wave -divider Write
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add wave -hex /testbench/PCW
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add wave -hex /testbench/InstrW
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add wave /testbench/InstrWName
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
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#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
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#add wave /testbench/dut/hart/ieu/dp/PCSrcE
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add wave -divider Regfile_signals
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#add wave /testbench/dut/uncore/dtim/memwrite
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#add wave -hex /testbench/dut/uncore/HADDR
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#add wave -hex /testbench/dut/uncore/HWDATA
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#add wave -divider
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#add wave -hex /testbench/PCW
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#add wave /testbench/InstrWName
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#add wave /testbench/dut/hart/ieu/dp/RegWriteW
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#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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#add wave -hex /testbench/dut/hart/ieu/dp/RdW
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add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
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add wave -divider Regfile_itself
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add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
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add wave -divider RAM
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#add wave -hex -r /testbench/dut/uncore/dtim/RAM
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add wave -divider Misc
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add wave -divider
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#add wave -hex -r /testbench/*
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-- Set Wave Output Items
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TreeUpdate [SetDefaultTree]
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WaveRestoreZoom {0 ps} {100 ps}
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 120
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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set DefaultRadix hexadecimal
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-- Run the Simulation
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#run 7402000
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#run 12750
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run -all
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#run 21400
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#quit
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Binary file not shown.
@ -26,7 +26,7 @@
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`include "wally-config.vh"
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module testbench();
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logic clk;
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logic reset;
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logic reset, reset_ext;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[10000:0];
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logic [`XLEN-1:0] signature[10000:0];
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@ -48,7 +48,7 @@ module testbench();
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// pick tests based on modes supported
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initial
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tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
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tests = {"../../tests/imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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@ -64,12 +64,18 @@ module testbench();
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flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.icache.FinalInstrRawF,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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/*
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.icache.controller.FinalInstrRawF,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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*/
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logic [`XLEN-1:0] PCW;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW);
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@ -86,7 +92,7 @@ module testbench();
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// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
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// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
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//dut.uncore.dtim.RAM[268437713]=64'b1;
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reset = 1; # 22; reset = 0;
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reset_ext = 1; # 22; reset_ext = 0;
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end
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// generate clock to sequence tests
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always
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@ -103,8 +109,11 @@ module testbench();
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end
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initial begin
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
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// $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
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// $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
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end
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endmodule
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@ -895,12 +895,12 @@ string imperas32f[] = '{
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// "rv32i_m/F/flt_b1-01", "6220",
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// "rv32i_m/F/flt_b19-01", "8ee0",
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"rv32i_m/F/flw-align-01", "2010",
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// "rv32i_m/F/fmadd_b1-01", "96860",
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"rv32i_m/F/fmadd_b1-01", "96860",
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"rv32i_m/F/fmadd_b14-01", "23d0",
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//--passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", "19bb30",
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"rv32i_m/F/fmadd_b16-01", "39d0",
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"rv32i_m/F/fmadd_b17-01", "39d0",
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// "rv32i_m/F/fmadd_b18-01", "4d10",
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"rv32i_m/F/fmadd_b18-01", "4d10",
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"rv32i_m/F/fmadd_b2-01", "4d60",
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"rv32i_m/F/fmadd_b3-01", "d4f0",
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"rv32i_m/F/fmadd_b4-01", "3700",
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