forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
commit
bbd17e730b
26
Makefile
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26
Makefile
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make all: submodules other
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submodules: addins/riscv-isa-sim addins/riscv-arch-test
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cd addins;git init; git submodule add https://github.com/riscv-non-isa/riscv-arch-test; git submodule add https://github.com/riscv-software-src/riscv-isa-sim
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git submodule update --init --recursive
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other:
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cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F
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cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D
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sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
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sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D/Makefile.include
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ifneq ("$(wildcard $(addins/riscv-isa-sim/build/.*))",)
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else
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mkdir addins/riscv-isa-sim/build
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endif
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cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin
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make -C addins/riscv-isa-sim/
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sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include
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echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include
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make -C tests/wally-riscv-arch-test
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make -C tests/wally-riscv-arch-test XLEN=32
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cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf
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make -C wally-pipelined/regression
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@ -1,6 +1,6 @@
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make all:
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make ../../tests/imperas-riscv-tests/
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make ../../tests/wally-riscv-arch-test/
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make XLEN=32 ../../tests/wally-riscv-arch-test/
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make -C ../../tests/imperas-riscv-tests/
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make -C ../../tests/wally-riscv-arch-test/
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make -C XLEN=32 ../../tests/wally-riscv-arch-test/
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exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf
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cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
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