Ross Thompson
2df18cc758
More bp/ifu pcmux cleanup.
2022-12-19 23:16:58 -06:00
Ross Thompson
565585b35a
Moved more muxes inside bp.
2022-12-19 22:51:55 -06:00
Ross Thompson
d8ee0ea59d
Begin cleanup of ifu. partial move of pc muxes inside bp.
2022-12-19 22:46:11 -06:00
David Harris
9fea16fd20
Simplified InstrRawD register
2022-12-19 15:18:42 -08:00
David Harris
a4da3f30e1
Explained hazard causes
2022-12-19 09:41:41 -08:00
David Harris
67763dbeec
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-12-19 09:09:57 -08:00
David Harris
3172dfd6a9
Properly decode fcvtint to prevent unnecessary stalls
2022-12-19 09:09:48 -08:00
Ross Thompson
159eda85f0
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
Alessandro Maiuolo
5a82898649
Added NumZeroE, AZeroM, and BZeroM
2022-12-18 20:02:40 -08:00
Alessandro Maiuolo
2989782fe6
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
2022-12-18 19:04:36 -08:00
Ross Thompson
4f56e6ff5d
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
73fd3fe040
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
ade06f3780
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
7d04675073
Cleanup comments.
2022-12-16 17:08:35 -06:00
Ross Thompson
89a30e7e37
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
41c636ecfa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-16 15:37:03 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
cturek
4b8cbd9fa0
Added integer support for initC
2022-12-16 19:02:11 +00:00
cturek
06c58f310d
Added mux for integer special case, renamed signals to match pipelined stage
2022-12-16 18:43:49 +00:00
David Harris
378c40002f
Clean up interrupt masking by Commit
2022-12-16 08:27:39 -08:00
David Harris
7989f449ad
Disabled starting FPU divider when IDIV_ON_FPU = 0
2022-12-16 06:35:29 -08:00
cturek
d7571bb9b1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-16 03:41:39 +00:00
David Harris
b7abc0037e
Use FlushE to reset integer divider FSM
2022-12-15 11:00:54 -08:00
David Harris
4365c99b52
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
David Harris
2457448e29
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
2022-12-15 08:23:34 -08:00
Ross Thompson
fa19a111c6
Hazard cleanup.
2022-12-15 10:05:17 -06:00
Ross Thompson
e774dd2db9
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
Ross Thompson
b02550b05c
Merge branch 'main' into hazards
2022-12-15 08:44:59 -06:00
David Harris
33aca5d35e
Added IDIV_ON_FPU flag to control whether integer division uses FPU
2022-12-15 06:37:55 -08:00
David Harris
5f637ef4a7
Use FPU divider for integer division when F is supported
2022-12-14 17:03:13 -08:00
cturek
8829e627eb
Fixed BZero and initU/initUM muxes
2022-12-14 16:44:46 +00:00
Ross Thompson
09dcb56217
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
a3ec829b80
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-14 09:34:34 -06:00
Ross Thompson
6da7849d27
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
cturek
ed59736a4b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-12-14 15:13:44 +00:00
Ross Thompson
1ba1bed0b0
Broken dont' use.
2022-12-11 23:24:01 -06:00
Ross Thompson
0716aedbd5
Removed unused flushf.
2022-12-11 16:28:11 -06:00
Ross Thompson
115e9e7bb3
Renamed CPUBusy to GatedStallF in IFU.
2022-12-11 15:54:19 -06:00
Ross Thompson
ffc5bce0b6
Renamed CPUBusy in LSU.
2022-12-11 15:52:51 -06:00
Ross Thompson
c50a2bd8bf
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
4aadd87679
Moved CPUBusy out of HPTW.
2022-12-11 15:48:00 -06:00
cturek
f57211bb49
Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
2022-12-10 21:56:35 +00:00
Ross Thompson
d15cf5c65c
Added comments about why it is not possible to use FlushWay and VictimWay directly.
2022-12-09 17:07:35 -06:00
Ross Thompson
1463e9b1d4
Finished merge of kip and ross's ifu fix.
2022-12-09 16:52:22 -06:00
Ross Thompson
6f01ea12e8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-12-09 16:42:16 -06:00
