cturek f57211bb49 Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs		2022-12-10 21:56:35 +00:00
..
cache	Added comments about why it is not possible to use FlushWay and VictimWay directly.	2022-12-09 17:07:35 -06:00
ebu	Moved all remaining bus logic from the LSU into ahbcacheinterface.	2022-11-11 14:30:32 -06:00
fpu	Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs	2022-12-10 21:56:35 +00:00
generic	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
hazard	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
ieu	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
ifu	Finished merge of kip and ross's ifu fix.	2022-12-09 16:52:22 -06:00
lsu	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
mmu	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
muldiv	code cleanup	2022-12-01 08:15:48 -08:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
uncore	Fixed the uart transmit fifo overrun bug.	2022-10-26 14:48:09 -05:00
wally	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00