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244 Commits

Author SHA1 Message Date
David Harris
d7be94fab2 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
cd02c894df renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
21526957cf Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
92c3cdc27d Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
96d6218078 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
acd920ae2f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
f7e64fcd69 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
Ross Thompson
171cf7413b Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Katherine Parry
de03954946 re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
Ross Thompson
f1bd2524b7 Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
334008630f Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686 Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
458bfbf6f6 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
5cd6c8069d signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
7d026e02f2 cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
706bc819e1 cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
0f586c9ed3 Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Ross Thompson
9868e685a4 Minor cleanup of cache. 2022-07-19 23:04:23 -05:00
Ross Thompson
6c8ac7851e Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Ross Thompson
ffda64587c Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Ross Thompson
a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
3670c47141 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
David Harris
f17501ed8c Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
3efbd2565a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
20bbe43a23 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
057524b840 Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
9e50c3440d sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
0df73d203b Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
Ross Thompson
396f697d2f Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
0a5b500aca Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
Ross Thompson
9dce2a0679 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
6e24a807f6 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
b7a680ec2a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
6d914def08 Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
Ross Thompson
7b96b3f73c Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
David Harris
2cea3349ad LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
Ross Thompson
6076f90bbc Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
Ross Thompson
e852cb8a31 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec More cache cleanup. 2022-02-13 12:38:39 -06:00
Ross Thompson
dd944265aa Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c More cache simplifications. 2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595 Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
David Harris
de5e80696d Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
5fd22caed4 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
f716cce832 Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
fdb4f909fc Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
88c7a94aa9 Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
7ff715f44f More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
7810a09782 Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
4a7ebb3757 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
4273775a2b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
David Harris
1479762ae9 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
e2191e3637 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
Ross Thompson
5c9e23527d cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
da2dca9816 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
161f907cae more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
359a23237d Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
188fe28691 more cleanup. 2022-02-07 13:29:19 -06:00
Ross Thompson
9510a33c15 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
708e0cf183 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
5539a5fa6f More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
6668956351 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
5536e3ca90 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
529d8b629a Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
41a79556e0 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
99f3d7a7f6 Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
45dc9c1ae6 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
0b66106925 More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
dd6baa9ed4 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
Ross Thompson
d21be9d998 Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
Ross Thompson
ea84211ff9 Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
290430cda8 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
725852362e Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
cdd599e340 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
459054900f Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
7c1f7e335c Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
ee3300bcd2 sram1rw cleanup 2022-02-03 18:03:22 +00:00
David Harris
97d31cec21 sram1rw cleanup 2022-02-03 17:50:23 +00:00
David Harris
f9dd79d3e3 cachereplacementpolicy cleanup 2022-02-03 17:19:14 +00:00
David Harris
034ff5462c cachereplacementpolicy cleanup 2022-02-03 17:18:48 +00:00
David Harris
65f3bf4e0a cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
eef04eed84 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
4d09510af9 cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
7f237220dd cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
a6708ed887 cache cleanup 2022-02-03 15:36:11 +00:00
Ross Thompson
42ef1e22e5 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
David Harris
325724f556 LSU Cleanup 2022-01-15 01:11:17 +00:00
David Harris
120fb7863f Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
David Harris
c97572d209 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-07 05:39:16 +00:00
David Harris
2a64b1bc95 Used .* in wrapper 2022-01-07 05:23:42 +00:00
Ross Thompson
0fddceffa6 Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 
assign from the input non translated virtual address.  Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address.  This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
 2022-01-06 23:19:09 -06:00
Ross Thompson
008ac20a43 Minor optimization to cache replacement. 2022-01-06 17:19:14 -06:00
Ross Thompson
e1db967417 Clean up of cachefsm. 2022-01-06 16:32:49 -06:00
Ross Thompson
d30ad136f3 cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv. 2022-01-05 22:56:18 -06:00
Ross Thompson
365b2715ed More name cleanup in cache. 2022-01-05 22:37:53 -06:00
Ross Thompson
77efcad15b Changed names of address in caches. 
Removed old cache files.
 2022-01-05 22:19:36 -06:00
Ross Thompson
8d33bf0b4a Slower but correct implementation of flush. 2022-01-05 16:57:22 -06:00
Ross Thompson
bd901cd125 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-05 14:15:27 -06:00
Ross Thompson
49eea2add5 Fixed bug with flush dirty not cleared in the correct cache line. 2022-01-05 14:14:01 -06:00
David Harris
32590d484c Removed more generate statements 2022-01-05 16:25:08 +00:00
David Harris
f04856ee94 Removed more generate statements 2022-01-05 16:01:03 +00:00
Ross Thompson
f89c1d91dc Renamed most signals inside cache.sv so they are agnostic to i or d. 2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd the i and d caches now share common verilog. 2022-01-04 23:40:37 -06:00
Ross Thompson
b06c3b8acd parameterized the caches with the goal of using common rtl for both i and d caches. 2022-01-04 22:40:51 -06:00
Ross Thompson
06168e67e4 Switched block for line in caches. 2022-01-04 22:08:18 -06:00
Ross Thompson
d94a1c6404 Fixed bug where last line of dcache was not written back to memory on dcache flush. 2022-01-04 21:55:48 -06:00
Ross Thompson
3c3c6d0fe8 Fixed dcache flush. 2022-01-04 18:40:58 -06:00
David Harris
1f07470477 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 19:47:51 +00:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00