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Fixed dcache flush.

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This commit is contained in:
Ross Thompson 2022-01-04 18:40:58 -06:00
parent 17b9143d10
commit 3c3c6d0fe8
1 changed files with 11 additions and 3 deletions
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14
pipelined/src/cache/dcache.sv vendored
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@ -104,6 +104,7 @@ module dcache
logic [INDEXLEN-1:0] FlushAdr;
logic [INDEXLEN-1:0] FlushAdrP1;
logic [INDEXLEN-1:0] FlushAdrQ;
logic FlushAdrCntEn;
logic FlushAdrCntRst;
logic FlushAdrFlag;
@ -127,7 +128,7 @@ module dcache
.d2(FlushAdr),
.s(SelAdrM),
.y(RAdr));
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
@ -207,20 +208,27 @@ module dcache
mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdrQ, {{OFFSETLEN}{1'b0}}}),
.s({SelFlush, SelEvict}),
.y(DCacheBusAdr));
// flush address and way generation.
// increment on 2nd to last way
flopenr #(INDEXLEN)
FlushAdrReg(.clk,
.reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn & FlushWay[NUMWAYS-1]),
.en(FlushAdrCntEn & FlushWay[NUMWAYS-2]),
.d(FlushAdrP1),
.q(FlushAdr));
assign FlushAdrP1 = FlushAdr + 1'b1;
flopenr #(INDEXLEN)
FlushAdrQReg(.clk,
.reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn),
.d(FlushAdr),
.q(FlushAdrQ));
flopenl #(NUMWAYS)
FlushWayReg(.clk,