Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

pipelined/regression/regression-wally.py

@@ -51,7 +51,7 @@ tc = TestCase(
       grepstr="400100000 instructions")
 configs.append(tc)
 
-tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a",  "imperas64c", "wally64priv"] # "wally64i", #,  "testsBP64"] 
+tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a",  "imperas64c", "wally64priv", "imperas64mmu"] # "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
   tc = TestCase(
         name=test,
@@ -59,7 +59,7 @@ for test in tests64gc:
         cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
-tests32gc = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a",  "imperas32c", "wally32priv"]  #"wally32i", 
+tests32gc = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a",  "imperas32c", "wally32priv", "imperas32mmu"]  #"wally32i", 
 for test in tests32gc:
   tc = TestCase(
         name=test,

pipelined/src/cache/dcache.sv

@@ -38,9 +38,10 @@ module dcache
    input logic 								FlushDCacheM,
    input logic [11:0] 						LsuAdrE, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0] 				LsuPAdrM, // physical address
+   input logic [11:0] 						PreLsuPAdrM, // physical or virtual address   
    input logic [`XLEN-1:0] 					FinalWriteDataM,
    output logic [`XLEN-1:0] 				ReadDataWordM,
-   output logic 							DCacheCommittedM,   
+   output logic 							DCacheCommittedM, 
 
    // Bus fsm interface
    input logic 								IgnoreRequest,
@@ -122,7 +123,7 @@ module dcache
 
   mux3 #(INDEXLEN)
   AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-			.d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** optimize change to virtual address.
+			.d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 			.d2(FlushAdr),
 			.s(SelAdrM),
 			.y(RAdr));

pipelined/src/cache/dcachefsm.sv

@@ -35,7 +35,7 @@ module dcachefsm
    // hazard inputs
    input logic 		  CPUBusy,
    input logic 		  CacheableM,
-   // hptw inputs
+   // interlock fsm
    input logic 		  IgnoreRequest,
    // Bus inputs
    input logic 		  DCacheBusAck,
@@ -143,6 +143,7 @@ module dcachefsm
 		  // PTW ready the CPU will stall.
 		  // The page table walker asserts it's control 1 cycle
 		  // after the TLBs miss.
+		  SelAdrM = 2'b01;
 		  NextState = STATE_READY;
 		end
 

pipelined/src/cache/icache.sv

@@ -32,7 +32,8 @@ module icache
    input logic 								CPUBusy,
 
    // mmu
-   input logic 								CacheableF,
+   //input logic 								CacheableF,
+   input logic [1:0] 						IfuRWF,
 
    // cpu side 
    input logic 								InvalidateICacheM,
@@ -161,7 +162,7 @@ module icache
 					   .IgnoreRequest,
 					   .ICacheBusAck,
 					   .ICacheFetchLine,
-					   .CacheableF,
+					   .IfuRWF,
 					   .hit,
 					   .SelAdr,
 					   .LRUWriteEn);

pipelined/src/cache/icachefsm.sv

@@ -27,31 +27,31 @@
 
 module icachefsm
   (// Inputs from pipeline
-   input logic 		  clk, reset,
+   input logic 		 clk, reset,
 
-   input logic 		  CPUBusy,
+   input logic 		 CPUBusy,
 
-   input logic 		  IgnoreRequest,
-   input logic 		  CacheableF,
+   input logic 		 IgnoreRequest,
+   input logic [1:0] IfuRWF,
 
    // BUS interface
-   input logic 		  ICacheBusAck,
+   input logic 		 ICacheBusAck,
 
    // icache internal inputs
-   input logic 		  hit,
+   input logic 		 hit,
 
    // Load data into the cache
-   output logic 	  ICacheMemWriteEnable,
+   output logic 	 ICacheMemWriteEnable,
 
    // Outputs to pipeline control stuff
-   output logic 	  ICacheStallF,
+   output logic 	 ICacheStallF,
 
    // Bus interface outputs
-   output logic 	  ICacheFetchLine,
+   output logic 	 ICacheFetchLine,
 
    // icache internal outputs
-   output logic       SelAdr,
-   output logic 	  LRUWriteEn
+   output logic 	 SelAdr,
+   output logic 	 LRUWriteEn
    );
 
   // FSM states
@@ -88,7 +88,7 @@ module icachefsm
 		  NextState = STATE_READY;
 		  ICacheStallF = 1'b0;
 		end
-		else if (CacheableF & hit) begin
+		else if (IfuRWF[1] & hit) begin
           ICacheStallF = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  if(CPUBusy) begin
@@ -97,7 +97,7 @@ module icachefsm
 		  end else begin
             NextState = STATE_READY;
 		  end
-        end else if (CacheableF & ~hit) begin
+        end else if (IfuRWF[1] & ~hit) begin
 		  SelAdr = 1'b1;                                         /// *********(
           NextState = STATE_MISS_FETCH_WDV;
         end else begin

pipelined/src/ifu/ifu.sv

@@ -240,10 +240,13 @@ module ifu (
 
   generate
 	if(`MEM_ICACHE) begin : icache
+	  logic [1:0] IfuRWF;
+	  assign IfuRWF = CacheableF ? 2'b10 : 2'b00;
+	  
 	  icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
 					.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
 					.ICacheFetchLine,
-					.CacheableF,
+					.IfuRWF(IfuRWF), //aways read
 					.PCNextF(PCNextFMux),
 					.PCPF(PCPF),
 					.PCF(PCFMux),

pipelined/src/lsu/lsu.sv

@@ -307,7 +307,7 @@ module lsu
   generate
     if(`MEM_DCACHE) begin : dcache
       dcache dcache(.clk, .reset, .CPUBusy,
-            .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM,
+            .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical
             .FinalWriteDataM, .ReadDataWordM, .DCacheStall,
             .DCacheMiss, .DCacheAccess, 
             .IgnoreRequest, .CacheableM, .DCacheCommittedM,