Ross Thompson 49eea2add5 Fixed bug with flush dirty not cleared in the correct cache line.		2022-01-05 14:14:01 -06:00
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cache.sv	Fixed bug with flush dirty not cleared in the correct cache line.	2022-01-05 14:14:01 -06:00
cachefsm.sv	Fixed bug with flush dirty not cleared in the correct cache line.	2022-01-05 14:14:01 -06:00
cachereplacementpolicy.sv	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
cacheway.sv	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
dcache_ptw_interaction_README.txt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
dcache.sv	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
dcachefsm.sv	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
icache.sv	parameterized the caches with the goal of using common rtl for both i and d caches.	2022-01-04 22:40:51 -06:00
icachefsm.sv	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
sram1rw.sv	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00