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cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.

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This commit is contained in:
Ross Thompson 2022-01-05 22:56:18 -06:00
parent 365b2715ed
commit d30ad136f3
2 changed files with 37 additions and 49 deletions
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4
pipelined/src/cache/cacheway.sv vendored
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@ -73,14 +73,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
genvar words;
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN))
CacheDataMem(.clk(clk), .Addr(RAdr),
.ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words]));
end
sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN))
CacheTagMem(.clk(clk),
.Addr(RAdr),
.ReadData(ReadTag),

82
pipelined/src/cache/sram1rw.sv vendored
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@ -1,73 +1,61 @@
/* -----\/----- EXCLUDED -----\/-----
// Depth is number of bits in one "word" of the memory, width is number of such words
///////////////////////////////////////////
// 1 port sram.
//
// Written: ross1728@gmail.com May 3, 2021
// Basic sram with 1 read write port.
// When clk rises Addr and WriteData are sampled.
// Following the clk edge read data is output from the sampled Addr.
// Write
//
// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
/-* verilator lint_off ASSIGNDLY *-/
// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
module sram1rw #(parameter DEPTH=128, WIDTH=256) (
input logic clk,
// port 1 is read only
input logic [$clog2(WIDTH)-1:0] Addr,
output logic [DEPTH-1:0] ReadData,
input logic [$clog2(DEPTH)-1:0] Addr,
output logic [WIDTH-1:0] ReadData,
// port 2 is write only
input logic [DEPTH-1:0] WriteData,
input logic [WIDTH-1:0] WriteData,
input logic WriteEnable
);
logic [WIDTH-1:0][DEPTH-1:0] StoredData;
logic [$clog2(WIDTH)-1:0] AddrD;
always_ff @(posedge clk) begin
AddrD <= Addr;
if (WriteEnable) begin
StoredData[Addr] <= #1 WriteData;
end
end
assign ReadData = StoredData[AddrD];
endmodule
/-* verilator lint_on ASSIGNDLY *-/
-----/\----- EXCLUDED -----/\----- */
// Depth is number of bits in one "word" of the memory, width is number of such words
/* verilator lint_off ASSIGNDLY */
module sram1rw #(parameter DEPTH=128, WIDTH=256) (
input logic clk,
// port 1 is read only
input logic [$clog2(WIDTH)-1:0] Addr,
output logic [DEPTH-1:0] ReadData,
// port 2 is write only
input logic [DEPTH-1:0] WriteData,
input logic WriteEnable
);
logic [WIDTH-1:0][DEPTH-1:0] StoredData;
logic [$clog2(WIDTH)-1:0] AddrD;
logic [DEPTH-1:0] WriteDataD;
logic [DEPTH-1:0][WIDTH-1:0] StoredData;
logic [$clog2(DEPTH)-1:0] AddrD;
logic [WIDTH-1:0] WriteDataD;
logic WriteEnableD;
always_ff @(posedge clk) begin
AddrD <= Addr;
WriteDataD <= WriteData;
WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay.
WriteEnableD <= WriteEnable;
if (WriteEnableD) begin
StoredData[AddrD] <= #1 WriteDataD;
end
end
assign ReadData = StoredData[AddrD];
endmodule
/* verilator lint_on ASSIGNDLY */