David Harris
057183bcc9
Cache code cleanup
2023-01-07 15:44:44 -08:00
David Harris
0a25f18a07
Cache code cleanup
2023-01-07 15:42:08 -08:00
David Harris
0ad707f1a5
Cache code cleanup
2023-01-07 15:39:13 -08:00
David Harris
d8f0425467
vclean working; started removing unused signals
2023-01-07 05:34:58 -08:00
Ross Thompson
b0d6c9616e
Minor optimizations.
2022-12-23 20:11:36 -06:00
David Harris
0a7ed944a5
Revert to 98b824
2022-12-22 23:58:14 -08:00
David Harris
d4bedca1bf
Code cleanup
2022-12-22 10:04:50 -08:00
Ross Thompson
c8c73f47d2
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
2022-12-21 22:13:05 -06:00
Ross Thompson
84f8d9953f
Updated cache fsm names to match book.
2022-12-21 16:49:53 -06:00
David Harris
e74d47bcb4
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
Ross Thompson
4f56e6ff5d
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
73fd3fe040
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
ade06f3780
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
89a30e7e37
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
9ebea891e2
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
dacba855da
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
09dcb56217
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
6da7849d27
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
Ross Thompson
c50a2bd8bf
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
3ddf509f28
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
d15cf5c65c
Added comments about why it is not possible to use FlushWay and VictimWay directly.
2022-12-09 17:07:35 -06:00
Ross Thompson
38adcb5b17
Minor simplification of cacheway way selection muxes.
2022-12-09 16:42:05 -06:00
Ross Thompson
9806babe9e
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
0fdbfb87eb
Removed commented code.
2022-12-05 17:21:56 -06:00
Ross Thompson
bcb927d172
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
2022-12-05 17:19:51 -06:00
Ross Thompson
2bcaacb179
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
b84b709182
Optimized way selection logic.
2022-12-04 12:30:56 -06:00
Ross Thompson
74d5ccc2b1
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
2022-12-04 01:20:51 -06:00
Ross Thompson
62e495c739
Moved selectedway mux into cacheway. It makes way more sense there.
2022-12-04 01:15:47 -06:00
Ross Thompson
e1ac736d43
Rename LineByteMux to FetchbufferbyteSel.
2022-12-04 01:00:04 -06:00
Ross Thompson
1d9b5badee
Properly flush cacheLRU.
2022-12-01 17:32:58 -06:00
Ross Thompson
cb310bfb1d
Removed unused port on cacheway.
2022-12-01 11:47:48 -06:00
Ross Thompson
813b2963fb
More optimization.
2022-11-30 11:26:48 -06:00
Ross Thompson
da7b13ba0a
Removed reset on dirty cache bits.
2022-11-30 11:04:37 -06:00
Ross Thompson
5e5cca6ae1
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
2022-11-30 11:01:25 -06:00
Ross Thompson
ac3e02692b
Preparing to merge dirty and tag srams.
2022-11-30 10:40:48 -06:00
Ross Thompson
8692ccbafb
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
Ross Thompson
e3577781b0
Optimization of cacheway.
2022-11-29 18:30:47 -06:00
Ross Thompson
9e4166407b
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
2022-11-29 14:51:09 -06:00
Ross Thompson
179d321683
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
1736983557
Cleanup cacheLRU.
2022-11-22 14:59:01 -06:00
Ross Thompson
2ae7b555be
File name change for cachereplacement policy to cacheLRU
2022-11-20 22:35:02 -06:00
Ross Thompson
84679c0062
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
a1f39a8186
Finally have the correct replacement policy implementation.
2022-11-17 17:36:37 -06:00
Ross Thompson
9b2236b2a0
Progress on the cache replacement policy implementation.
2022-11-16 15:35:34 -06:00
Ross Thompson
5f7b0b8a9b
Oups found a bug with my cache changes. I took TrapM out of the logic path for selecting the cache's address CAdr (previously RAdr) to improve the critical path. This is fine for the dcache because both the E and M stages are flushed. However for the ICache only F is flushed. PCNextF is valid and points to XTVEC so the cache must take NextAdr rather than PAdr as CAdr.
2022-11-16 12:36:58 -06:00
