cvw/pipelined/src/cache
2023-01-07 15:44:44 -08:00
..
cache.sv Cache code cleanup 2023-01-07 15:44:44 -08:00
cachefsm.sv Minor optimizations. 2022-12-23 20:11:36 -06:00
cacheLRU.sv I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
cacheway.sv Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
subcachelineread.sv Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00