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233 Commits

Author SHA1 Message Date
Rose Thompson
46fdfde7ec Removed unnecessary display from testbench. 2024-04-06 16:10:18 -05:00
David Harris
e8111da88a Removed unused old regression-wally 2024-04-06 13:47:44 -07:00
David Harris
6b844a2e6e Added GUI support and removed unused wave files 2024-04-06 13:43:06 -07:00
David Harris
3c855e3e90 Passing arguments to buildroot, not yet checking result correctly 2024-04-06 11:42:41 -07:00
David Harris
b3f007ec7f Working on buildroot in regression 2024-04-06 11:11:22 -07:00
David Harris
ac9a21873d Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test 2024-04-06 10:34:21 -07:00
slmnemo
d107a42e8c Replaced rewrite command with system rm command for uart file. Fixed comment on line 573 2024-04-05 21:39:41 -07:00
slmnemo
2fcae601a9 Replaced funky rewrite call with file removal 2024-04-05 20:59:08 -07:00
slmnemo
3ee25c8936 Merged testbench changes 2024-04-05 17:20:03 -07:00
slmnemo
5378b61eb2 Added UART output file buildroot_uart.out for Linux test 'buildroot'. 2024-04-05 17:18:03 -07:00
Divya2030
aa6eacbce5
Merge branch 'openhwgroup:main' into main 2024-04-03 10:40:30 -07:00
Divya2030
135f3b6f8f vcs testbench 2024-04-03 10:39:02 -07:00
David Harris
8755966f50 Incorporated Kunlin's Verilator hack so testbench runs 110x faster. Isolated within ifdef VERILATOR to make it easier to remove when Verilator issue 4967 is resolved 2024-04-03 07:23:02 -07:00
David Harris
8741b01818 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-04-03 06:51:24 -07:00
David Harris
929eb0430c Testbench uses posedge control signals to speed up Verilator 2024-04-03 06:51:18 -07:00
Rose Thompson
c11d7ea55e Fixed bug in the testbench which did not allow external memory to work correctly. 2024-04-01 10:59:40 -05:00
David Harris
0caab3c0c9 Removed delays from cacheLRU and testbench 2024-03-25 12:20:25 -07:00
David Harris
b4a914a6e3 Commented out fcvt.h.l tests that don't run on fh_arch64gc arch64zfh; added testbench feature to print when the program jumps to address 0, presumably a bad trap handler 2024-03-14 21:53:30 -07:00
Rose Thompson
3cf6a19729
Merge branch 'main' into main 2024-03-10 10:48:21 -05:00
Rose Thompson
24dffa39d5 Yay. David and I got our first Quad load/store instructions working! 2024-03-07 12:48:52 -06:00
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
KelvinTr
01c45ab9d7 Fixed K extension changes 2024-02-28 17:05:08 -06:00
Rose Thompson
83dc9cd926 More cleanup. 2024-02-07 15:53:40 -06:00
Rose Thompson
0d008c9281 Merge branch 'main' of https://github.com/openhwgroup/cvw 
Plus major cleanup of wally-batch.do
 2024-02-07 15:44:38 -06:00
Rose Thompson
2acbc95b72 Partially got linux imperas boot working in the main testbench. 2024-02-07 15:38:18 -06:00
Rose Thompson
7f3877f076 Finally have buildroot running in the main testbench! 2024-02-07 11:23:46 -06:00
David Harris
e7364290e3 Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage 2024-02-07 06:27:53 -08:00
Rose Thompson
812c169132 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-02-06 22:07:09 -06:00
Rose Thompson
5ab88a5daa Updated to simplify configOptions. 2024-02-06 22:07:06 -06:00
David Harris
d71efedab5
Merge pull request #619 from ross144/main 
Merged all regression tests except imperas linux boot into testbench.sv.
 2024-02-06 16:19:42 -08:00
Rose Thompson
da65928f04 Fixed issue with branch deriv configs. 2024-02-06 16:07:41 -06:00
David Harris
dfee790ad7 Fixed derivative generation when derivs don't already exist. Fixed lint to print success when no failures. Added Zfh fma tests. Some fp tests not running yet. 2024-02-06 12:35:56 -08:00
Rose Thompson
58580445ab Only output instruction count when the csrs are implemented. 2024-02-05 14:42:27 -06:00
Rose Thompson
8b5970fdc4 Buildroot now reports every 100K instructions as before. 2024-02-05 13:19:48 -06:00
Rose Thompson
c9176f108e Fixed paths to buildroot objdump label and addr files. 2024-02-05 13:09:31 -06:00
Rose Thompson
17380a68d5 Moved buildroot testbench to the main testbench. 
However I don't have a positive control or negative indicator to
say when the test completes or passes.
 2024-02-05 13:03:48 -06:00
Rose Thompson
44e87f3e3e First cut at removing the linux testbench and merging build root into the main testbench. 2024-02-05 12:46:14 -06:00
David Harris
66c1c71a56 Coverage improvements 2024-02-04 18:56:40 -08:00
Rose Thompson
d59daf9a6f Fixed odd bug in the testbench which wasn't skipping signature check for coverage tests. 2024-02-01 12:22:28 -06:00
David Harris
49714cb282 Fixed assertions to throw fatal error, improved nightly regression to have passing cases 2024-01-31 21:39:18 -08:00
David Harris
111f592613 factor divsqrt out of floating-point test cases to run on more derived configs 2024-01-31 14:52:15 -08:00
David Harris
17c9be7695 Cleanup typos, remove Zicond from riscof until it is working 2024-01-18 21:36:52 -08:00
David Harris
0588d611ea Zfa fli support working for F and D 2024-01-16 17:27:40 -08:00
David Harris
da4eca4854 Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int. 2024-01-15 13:24:57 -08:00
David Harris
9eb6d9c8b8 Added Zicond support 2024-01-11 07:37:15 -08:00
David Harris
d93684be21 Verilate running (slowly) 2024-01-07 21:30:33 -08:00
David Harris
7cd02351d9 Updated testbench to count size of signature without searching for x. Now runs with Verilator. 2024-01-07 09:00:19 -08:00
David Harris
caedab679a Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x 2024-01-07 07:14:12 -08:00
David Harris
34f97201ee Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-01-06 08:19:56 -08:00
David Harris
167e061a1c Fixed truncated begin_signature in testbench 2024-01-06 08:19:46 -08:00
Rose Thompson
ab07d64195 Fixes coremark. Maybe works with verilator. 2024-01-06 00:41:57 -06:00
David Harris
ed623f1a71 Fixed unsupported riscof YAML string; preparing for Verilator -G testcase 2024-01-05 20:06:21 -08:00
David Harris
8552369687 Merged PR538, delete unused tests 2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019 All regression tests which matter are running! 2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59 Updated tests with ending label. 2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89 Reverted logic to bit change. 2023-12-20 13:16:32 -06:00
Rose Thompson
a8ab3c8342 Ok that is a stange bug. 
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
 2023-12-20 12:25:34 -06:00
Rose Thompson
9ee1ffe8fe Almost working with modelsim and verilator. 2023-12-20 11:29:31 -06:00
David Harris
5dbca251d8 Defined new Zicboz and Zcb tests 2023-12-19 13:24:11 -08:00
Rose Thompson
2e792606dd More progress. Most tests are passing in modelsim. 2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3 Progress. 2023-12-18 20:23:19 -06:00
Rose Thompson
1e1759c258 Restored the one hack change which prevents verilator from working. 2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b Yay! I got verilator to compile our testbench! Does it actually work I don't know. 2023-12-18 16:44:34 -06:00
Rose Thompson
c1ac153a4f Closer to verilator support. 2023-12-18 16:26:56 -06:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
David Harris
38f4d9baf8 Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e 2023-12-15 05:05:53 -08:00
David Harris
68d96a929c Fixed hierarchical path to EcallFaultM in testbench 2023-12-13 16:37:54 -08:00
David Harris
ff26baf7e8 Rolled back attempt to support Verilator 2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator 2023-12-13 11:33:59 -08:00
Jacob Pease
a1e7158bd9 Merge branch 'main' of github.com:openhwgroup/cvw 2023-11-18 19:20:48 -06:00
Rose Thompson
38b327eaf8 Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters. 2023-11-17 11:21:25 -06:00
Jacob Pease
23e5fca2a7 Merge branch 'main' of github.com:jacobpease/cvw 2023-11-16 14:04:11 -06:00
Rose Thompson
da59cb71a9 Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config. 2023-11-13 14:12:27 -06:00
David Harris
4de21c206f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-03 16:04:10 -07:00
David Harris
dd072c80f2 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
naichewa
a08356fdaa correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
naichewa
e3d8162279 harris code review 3 2023-11-01 10:14:15 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
Jacob Pease
3e891ee635 Merge branch 'main' of github.com:openhwgroup/cvw 2023-10-17 14:13:28 -05:00
Jacob Pease
2b1c604016 Slight modification to testbench.sv 2023-10-17 14:13:18 -05:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
4941fe1769 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
fab9fbd7f1 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
Rose Thompson
c1d6fddea8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
9a49ec0b98 Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
7f79c0a855 Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
Ross Thompson
4d76e83318 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
Ross Thompson
f3d35f914a Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
af046d4772 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Ross Thompson
301d54fea8 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83 Removed old configs from function name module. 2023-06-14 16:35:55 -05:00