Noah Boorstin
03cea6e29b
more misaligned read fixing
...
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
2021-01-28 16:14:35 -05:00
David Harris
3e786729ac
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 15:44:14 -05:00
David Harris
1ad69b52d5
Fixed floating signals in clint and ieu
2021-01-28 15:44:05 -05:00
Noah Boorstin
e65166bec5
busybear testbench: understand bytemask for writes
2021-01-28 15:42:47 -05:00
Noah Boorstin
699bc7e195
Make gdb output parser understand other varients of load/store
2021-01-28 15:35:41 -05:00
David Harris
8eebf01dca
Fixed c.jr instruction improperly writing ra
2021-01-28 15:18:23 -05:00
Noah Boorstin
9a45b49536
busybear: ret is only 1 word
2021-01-28 14:47:40 -05:00
Noah Boorstin
5a5237b908
add speculative exception for compressed instructions
2021-01-28 14:40:35 -05:00
Noah Boorstin
632fecf43a
testbench now understands lw not aligned to 8 bytes
...
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
2021-01-28 13:33:22 -05:00
Noah Boorstin
e19af0a52a
busybear testbench: check for read data address also
...
and check for more end of files better
2021-01-28 13:16:38 -05:00
Noah Boorstin
7fd73d12e9
update busybear testbench to conform to new structure
2021-01-28 01:21:47 -05:00
Noah Boorstin
be3d024527
Busybear test now processes first 100 instrs correctly!
...
- changed test parser to recognize lw in addition to lw
also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
Noah Boorstin
ed85fda42a
fix memory write address decoding for busybear tests
2021-01-28 01:19:26 -05:00
David Harris
52d6a01cea
Created DCU and moved memdp into DCU
2021-01-28 01:03:12 -05:00
David Harris
01e37210ea
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-28 00:22:11 -05:00
David Harris
af25784b61
Provided PC + 2 or 4 (PCLink) for JAL
2021-01-28 00:22:05 -05:00
Noah Boorstin
840528a05f
update busybear testbench to conform to new structure
2021-01-27 23:42:19 -05:00
David Harris
9d821aab0f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 22:49:55 -05:00
David Harris
37a58cea17
Repartitioned with Instruction Fetch Unit, Integer Execution Unit
2021-01-27 22:49:47 -05:00
Noah Boorstin
74e57a8472
update busybear testbench to conform to new structure
2021-01-27 12:54:09 -05:00
David Harris
db5f45c240
Moved privileged unit from datapath to hart
2021-01-27 07:46:52 -05:00
David Harris
092edf953e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-27 06:40:39 -05:00
David Harris
4318629b32
Repartitioned datapath and controller into ieu
2021-01-27 06:40:26 -05:00
Noah Boorstin
91564c7ab1
show instruction assembly in waveform
2021-01-26 12:34:12 -05:00
Noah Boorstin
91dcffa26f
Update busybear tests to conform to new directory structure
2021-01-25 20:37:18 -05:00
Noah Boorstin
09c92a6b5d
Fixed mem write checking
...
now passes around 50 instructions!
2021-01-25 20:07:08 -05:00
Noah Boorstin
05d4f2d33d
fix speculation ignoring for PC fetching
2021-01-25 20:07:06 -05:00
David Harris
b7988e536f
Reset Vector moved to config file
2021-01-25 15:57:36 -05:00
Teo Ene
a54070d074
Added synth and PnR flow
2021-01-25 14:28:14 -06:00
David Harris
bf07ec92b5
Added test configurations
2021-01-25 11:28:43 -05:00
Noah Boorstin
1d71282332
small busybear testbench changes
2021-01-24 20:43:47 -05:00
Noah Boorstin
7afa48d4ea
Linux testbench works now
...
Added parameterized PCSTART to allow compatibility between imperas and busybear tests
Hopefully we are done with the "busybear" branch, please don't use it for future work
2021-01-24 17:10:00 -05:00
Noah Boorstin
c7e2259af0
Merge branch 'busybear' into main
...
Merging busybear testbench into main, keeping main edits of wally src
2021-01-24 16:28:36 -05:00
Noah Boorstin
e200000f74
handle "zero" as 0 properly
2021-01-24 01:03:45 -05:00
Noah Boorstin
405cc14b56
Start on checking mem writes
...
Also i'm so sorry for messing up git today
Now testing with first 100 instrs instead of first 30
because no memory writes happen in the first 30
2021-01-24 00:58:22 -05:00
David Harris
056cd03efd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-24 00:52:06 -05:00
David Harris
2046b810fc
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 21:31:06 -08:00
David Harris
ff4da36e3d
Cleaned up regfile x0 tied to gnd
2021-01-23 21:30:54 -08:00
David Harris
468fa7528f
Initial checkin of UART
2021-01-23 21:29:18 -08:00
Noah Boorstin
6d84658369
sucessfully simulate first 30 instructions
...
still need to find a better solution to InstrAccessFault/DataAccessFault though
2021-01-23 19:01:44 -05:00
Noah Boorstin
71883dca82
More linux testbench fixes
...
So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(
This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.
Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
2021-01-23 17:52:05 -05:00
Noah Boorstin
117713be89
Linux test now gets through first 8 instructions!
...
fixes the python parser:
get the value, not function name, of PC
only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
2021-01-23 16:46:45 -05:00
David Harris
b77ef491fc
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 10:48:12 -05:00
David Harris
556e815c4b
Cleaned up regfile x0 tied to gnd
2021-01-23 10:22:20 -05:00
David Harris
c6c5dcb2ef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-23 10:19:28 -05:00
David Harris
b28129fcc3
Initial checkin of UART
2021-01-23 10:19:09 -05:00
Noah Boorstin
a66bd9008c
slightly more info on errors, add instruction decoding
2021-01-22 21:14:45 -05:00
Noah Boorstin
cdcacb8dbe
change how testbench reads data
...
we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
2021-01-22 20:27:01 -05:00
Noah Boorstin
379fc6d5ca
change regfile to not hold state of x0
2021-01-22 15:12:33 -05:00
Noah Boorstin
adfeb29b77
change regfile to not hold state of x0
2021-01-22 15:11:55 -05:00
