Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-23 13:04:28 +00:00
Code Issues Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
19 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
cdcacb8dbe
Go to file
Noah Boorstin cdcacb8dbe change how testbench reads data 
we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
2021-01-22 20:27:01 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined change how testbench reads data 2021-01-22 20:27:01 -05:00
.gitignore load instructions from file line by line 2021-01-22 14:11:17 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor