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Configurable RISC-V Processor
24 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
405cc14b56
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Noah Boorstin 405cc14b56 Start on checking mem writes 
Also i'm so sorry for messing up git today

Now testing with first 100 instrs instead of first 30
because no memory writes happen in the first 30
2021-01-24 00:58:22 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined sucessfully simulate first 30 instructions 2021-01-23 19:01:44 -05:00
.gitignore load instructions from file line by line 2021-01-22 14:11:17 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor