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Configurable RISC-V Processor
20 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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David Harris 056cd03efd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-24 00:52:06 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh 2021-01-23 10:48:12 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor