Harshini Srinath
09ac5b1817
Update pmpadrdec.sv
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Program clean up
2023-06-12 18:41:47 -07:00
Harshini Srinath
ccb81c84f4
Update pmachecker.sv
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Program clean up
2023-06-12 18:39:36 -07:00
Harshini Srinath
5a6a932b7e
Update mmu.sv
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Program clean up
2023-06-12 18:36:04 -07:00
Harshini Srinath
a57a619349
Update hptw.sv
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Program clean up
2023-06-12 18:31:38 -07:00
Harshini Srinath
ec0454111f
Update adrdecs.sv
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Program clean up
2023-06-12 18:22:32 -07:00
Harshini Srinath
b1ee6bfde5
Update adrdec.sv
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Program clean up
2023-06-12 17:28:21 -07:00
Harshini Srinath
7c51dd18dd
Update mul.sv
2023-06-12 14:00:37 -07:00
Harshini Srinath
08459c4cc4
Update mdu.sv
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Program clean up
2023-06-12 13:54:54 -07:00
Harshini Srinath
bdd2206817
Update div.sv
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Program clean up
2023-06-12 13:47:09 -07:00
Harshini Srinath
15928c5d7b
Update swbytemask.sv
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Program clean up
2023-06-12 13:37:35 -07:00
Harshini Srinath
f3a7d9030c
Update subwordwrite.sv
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Program clean up
2023-06-12 13:35:27 -07:00
Harshini Srinath
f1f21f0896
Update subwordread.sv
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Program clean up
2023-06-12 13:31:54 -07:00
Harshini Srinath
4d0be994aa
Update lsu.sv
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Program clean up
2023-06-12 13:29:18 -07:00
Harshini Srinath
a45f2fd044
Update lrsc.sv
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Program clean up
2023-06-12 13:14:36 -07:00
Harshini Srinath
d21fd3da44
Update dtim.sv
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Program clean up
2023-06-12 13:11:24 -07:00
Harshini Srinath
048e100805
Update atomic.sv
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Program clean up
2023-06-12 13:08:54 -07:00
Harshini Srinath
ec1aa29edc
Update amoalu.sv
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Program clean up
2023-06-12 12:54:50 -07:00
Harshini Srinath
9d0fc0a138
Update spill.sv
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Program clean up
2023-06-12 12:50:11 -07:00
Harshini Srinath
19e8acff70
Update irom.sv
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Program clean up
2023-06-12 12:44:09 -07:00
Harshini Srinath
a5561c2cf6
Update ifu.sv
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Program clean up
2023-06-12 12:38:52 -07:00
Harshini Srinath
b5c655b1c3
Update decompress.sv
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Program clean up
2023-06-12 12:27:55 -07:00
Harshini Srinath
d0ede93dc1
Update CodeAligner.py
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Program clean up
2023-06-12 12:25:47 -07:00
Harshini Srinath
5f73c9727f
Update shifter.sv
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Program clean up
2023-06-12 12:23:45 -07:00
Harshini Srinath
0f36cbd830
Update regfile.sv
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Program clean up
2023-06-12 12:21:25 -07:00
Harshini Srinath
f1cef043c6
Update ieu.sv
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Program clean up
2023-06-12 12:19:04 -07:00
Harshini Srinath
304adcb9b0
Update extend.sv
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Program clean up
2023-06-12 12:15:33 -07:00
Harshini Srinath
1d24a9c912
Update datapath.sv
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Program clean up
2023-06-12 12:13:58 -07:00
Ross Thompson
ee4352975c
This parameterizes the testbench but does not use the verilator updates or the new testbench.
2023-06-12 11:00:30 -05:00
Ross Thompson
7031a7b1ea
Merge pull request #327 from harshinisrinath1001/main
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Fixed the spacing in the fpu module
2023-06-12 11:53:52 -04:00
Harshini Srinath
0c324bce7b
Update prioritythermometer.sv
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Program clean up
2023-06-11 19:18:21 -07:00
Harshini Srinath
66856f31ca
Update or_rows.sv
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Program clean up
2023-06-11 19:16:37 -07:00
Harshini Srinath
250ea7668e
Update neg.sv
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Program clean up
2023-06-11 19:15:28 -07:00
Harshini Srinath
5a40272fd7
Update counter.sv
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Program clean up
2023-06-11 19:12:57 -07:00
Harshini Srinath
16028a5766
Update adder.sv
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Program clean up
2023-06-11 19:09:18 -07:00
Harshini Srinath
61b85d1c7f
Update unpackinput.sv
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Program clean up
2023-06-11 17:09:11 -07:00
Harshini Srinath
37ad074c4d
Update fctrl.sv
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Program clean up
2023-06-11 17:03:29 -07:00
Harshini Srinath
ac17b93a84
Update fcmp.sv
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Program clean up
2023-06-11 16:54:52 -07:00
Harshini Srinath
c19ba6c3f4
Update fsgninj.sv
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Program clean up
2023-06-11 16:52:00 -07:00
Harshini Srinath
cf39819bac
Update fregfile.sv
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Program clean up
2023-06-11 16:49:20 -07:00
Harshini Srinath
a98096aa7d
Update fpu.sv
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Program clean up
2023-06-11 16:43:31 -07:00
Harshini Srinath
4c4e6ca520
Update fhazard.sv
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Program clean up
2023-06-11 16:06:44 -07:00
Harshini Srinath
610ac81a71
Update fcvt.sv
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Program clean up
2023-06-11 16:05:14 -07:00
Harshini Srinath
e469e4fd20
Update fcvt.sv
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Program clean up
2023-06-11 15:59:20 -07:00
Ross Thompson
e27dfb8ce0
Merge branch 'verilator'
2023-06-11 15:28:04 -05:00
David Harris
29b48334d8
Fixed lint errors, presumably detected by latest version of verilator
2023-06-11 06:48:42 -07:00
David Harris
99fe09fb40
Merge pull request #322 from harshinisrinath1001/main
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Fixing spacing for ebu
2023-06-11 06:00:35 -07:00
Harshini Srinath
aead7cbe49
Update fctrl.sv
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Program clean up
2023-06-10 19:38:50 -07:00
Harshini Srinath
04a744c249
Update fcmp.sv
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Program clean up
2023-06-10 19:35:58 -07:00
Harshini Srinath
ffada57ea2
Update fcmp.sv
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Program clean up
2023-06-10 19:34:58 -07:00
Harshini Srinath
ec188987b8
Update fclassify.sv
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Program clean up
2023-06-10 19:30:18 -07:00
Harshini Srinath
9dc72c9e54
Update controllerinput.sv
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Program clean up
2023-06-10 18:26:06 -07:00
Harshini Srinath
dbdb3c69d3
Update ahbinterface.sv
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Program clean up
2023-06-10 18:18:16 -07:00
Harshini Srinath
dc0b95c4ac
Program clean up
2023-06-10 18:13:40 -07:00
Ross Thompson
c7536663c0
Merge pull request #319 from davidharrishmc/dev
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Renamed Performance Counter extension
2023-06-09 21:21:45 -04:00
David Harris
b70b0c7c5e
Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
2023-06-09 14:40:01 -07:00
David Harris
df96900aa1
Added named support for Zicntr and Zihpm
2023-06-09 09:35:51 -07:00
Harshini Srinath
aafa5d6ec3
Update ebu.sv
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Code clean up
2023-06-09 08:53:27 -07:00
Harshini Srinath
570a628198
Update subcachelineread.sv
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Code clean up
2023-06-09 08:50:51 -07:00
Harshini Srinath
c49232f0d2
Update cacheway.sv
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Code clean up
2023-06-09 08:48:11 -07:00
Harshini Srinath
e7fb7403ef
Update cacheLRU.sv
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Code clean up
2023-06-09 08:43:38 -07:00
Harshini Srinath
19c1a0f99b
Update cache.sv
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Formatting clean up
2023-06-09 08:39:57 -07:00
Ross Thompson
a8a8422557
Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.
2023-06-09 09:28:24 -05:00
David Harris
75dc86ddc0
Merge pull request #313 from ross144/main
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Fix extraneous force in testbench which keep btb in reset.
2023-06-06 08:41:34 -07:00
David Harris
c9ca5108b1
Merge pull request #312 from ross144/main
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Fixed typo in coremark makefile.
2023-06-06 05:44:22 -07:00
Ross Thompson
918464c236
Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
2023-06-05 15:42:05 -05:00
James Stine
3bd5bbce48
Update some spacing to make it look better
2023-06-05 11:03:06 -05:00
Ross Thompson
1ceea51d8b
Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet.
2023-05-31 16:51:00 -05:00
Ross Thompson
a963f0af3a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
169539f773
Cleanup parameterization for verilator 5.010.
2023-05-31 10:02:34 -05:00
Ross Thompson
8e1476cb8c
Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt.
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This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
2023-05-30 15:20:24 -05:00
Ross Thompson
04d0fd94f0
Merge branch 'param-lim-merge'
2023-05-26 16:25:35 -05:00
Ross Thompson
3cc85349b5
Uncore is now parameterized.
2023-05-26 16:24:12 -05:00
Ross Thompson
1315a0bf4a
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Ross Thompson
f1b8689955
Finished fpu parameterization using Lim's method.
2023-05-26 14:40:06 -05:00
Ross Thompson
29e0357f21
fdiv is now parameterized using Lim's method.
2023-05-26 14:25:14 -05:00
Ross Thompson
81491e85e5
Parameterized fpu's unpack and fma using Lim's method.
2023-05-26 14:12:25 -05:00
Ross Thompson
c7e515634d
I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types.
2023-05-26 13:56:51 -05:00
Ross Thompson
b517a96261
Update top level parameterized. Simulation slowed down to 4.5 minutes.
2023-05-26 12:13:11 -05:00
Ross Thompson
8cf38b28aa
The privileged unit is parameterized using Lim's method.
2023-05-26 12:03:46 -05:00
Ross Thompson
4d961bd080
Completed LSU parameterization based on Lim's changes.
2023-05-26 11:26:09 -05:00
Ross Thompson
d37e010aa4
Subwordread now parameterized.
2023-05-26 11:22:44 -05:00
Ross Thompson
02a788a083
PMA checker's address decoder is now parameterized. I did not see bit slicing in Lim's code. I'm not sure how they got around this issue.
2023-05-26 11:06:48 -05:00
Ross Thompson
0e1131d190
Progress on LSU.
2023-05-26 10:47:09 -05:00
Ross Thompson
0020d94b39
Updated mmu's tlb and hptw to use Lim's parameterization.
2023-05-24 18:02:22 -05:00
Ross Thompson
70c8828ac2
PM(P/A) checkers parameterized based on Lim's work.
2023-05-24 17:20:55 -05:00
Ross Thompson
fcb1c63f5f
Partial parameterization into mmu.
2023-05-24 16:12:41 -05:00
Ross Thompson
5f5f33787d
MDU and hazard unit now also parameterized. Based on Lim's work. Again I want to clarify this their work. Not mine. I'm just doing this because the merge had an issue.
2023-05-24 15:01:35 -05:00
Ross Thompson
1299319d0b
More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.
2023-05-24 14:56:02 -05:00
Ross Thompson
052bc95966
More parameterization. Copied Lim. Still no slow down.
2023-05-24 14:49:22 -05:00
Ross Thompson
b91b54589e
Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down.
2023-05-24 14:05:44 -05:00
Ross Thompson
6d2e3070a5
Merged changes.
2023-05-24 13:15:52 -05:00
Ross Thompson
80aa0888f3
Updated headers to local branch history predictors.
2023-05-24 12:52:42 -05:00
Ross Thompson
930fb67308
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
Ross Thompson
69a9bf7055
Adds local history predictor.
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Fixes performance counters, but not coremark.
2023-05-23 18:53:46 -05:00
Ross Thompson
664231c0da
Merge branch 'localhistory'
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Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
2023-05-22 10:13:31 -05:00
Ross Thompson
625d365f3e
Fixes load and store stall counters.
2023-05-22 10:08:49 -05:00
Ross Thompson
8f305bf3cf
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-05-11 14:56:53 -05:00
Ross Thompson
d545a2ec74
Partially working local history repair.
2023-05-11 14:56:26 -05:00
Ross Thompson
3a98fb8680
Baseline localhistory with speculative repair built.
2023-05-05 15:23:45 -05:00
Ross Thompson
42517bae6f
Fixed bug in local history predictor.
2023-05-04 16:54:41 -05:00
