David Harris
fd5e492b2a
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-02-01 20:47:20 -08:00
Jordan Carlin
8633f263a2
Complete coverage of tlb camlines in IFU
2024-02-01 20:41:05 -08:00
David Harris
efdc571f59
Removed redundant assertion
2024-02-01 20:14:40 -08:00
Rose Thompson
d59daf9a6f
Fixed odd bug in the testbench which wasn't skipping signature check for coverage tests.
2024-02-01 12:22:28 -06:00
David Harris
49714cb282
Fixed assertions to throw fatal error, improved nightly regression to have passing cases
2024-01-31 21:39:18 -08:00
David Harris
111f592613
factor divsqrt out of floating-point test cases to run on more derived configs
2024-01-31 14:52:15 -08:00
David Harris
bf7e20e846
IEEE754 derivatives for testfloat
2024-01-30 09:49:27 -08:00
James E. Stine
0d9e2fdf60
update Boolean logic for all testing for divide
2024-01-29 17:37:35 -06:00
James E. Stine
95a97faf3f
Fixes testbench issues in testing against all vectors. Still a bug in ui32_to_f16_rz.sv - but will fix. Some things can be optimized. Overall, adds a FSM to test things more effectively. Actually is faster than previously as it assumed everything took the same number of cycles. Again, some things can be optimized
2024-01-29 16:46:34 -06:00
David Harris
171430a695
FPU and PMP tests
2024-01-21 14:41:22 -08:00
David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
David Harris
74b242ce5c
Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow
2024-01-17 12:25:06 -08:00
David Harris
4cfc86140c
Zfa fmvh complete and passing tests:
2024-01-17 06:18:00 -08:00
David Harris
07e7e02241
Coded Zfa fmvp but no tests exist
2024-01-16 21:26:42 -08:00
David Harris
8654375f26
Zfa fminm/fmaxm/fltq/fleq implemented and tested
2024-01-16 20:03:54 -08:00
David Harris
0588d611ea
Zfa fli support working for F and D
2024-01-16 17:27:40 -08:00
David Harris
1a77c08f6e
Fixed issues 575 and 477 about FPU tests failing when Zfh = 1.
2024-01-16 10:46:44 -08:00
David Harris
0d56a281b9
Cleaned up indentation in testbench-fp
2024-01-15 13:25:46 -08:00
David Harris
da4eca4854
Tested Zfh support using unreleased version of risch-arch-test Zfh tests. Fixed two bugs in fmv to/from int.
2024-01-15 13:24:57 -08:00
David Harris
9e78a7e290
Incorporated jstine fixes of FPU special case and testbench for conversion
2024-01-15 07:25:08 -08:00
David Harris
6226c3db96
Revert "Fixes for Issue #541 "
2024-01-12 07:50:13 -08:00
James E. Stine
dbe8394651
Update testbench-fp.sv to check result and flags for cvtint and cmp. This addresses fix for Issue #541 . It also adds a temporary fix to avoid issues between tests. This will be fixed in an upcoming push where we use scanf instead of readmemh to help keep compatibility with Verilator. Additional testing is needed of new testbench-fp.sv before can push in new tb with scanf
2024-01-12 00:32:18 -06:00
David Harris
9eb6d9c8b8
Added Zicond support
2024-01-11 07:37:15 -08:00
James E. Stine
828d6bc619
more optimized check on Issue #546
2024-01-09 09:22:39 -06:00
James E. Stine
cfb27de8a3
Fix Issue #541 where FlagMatch was not added which I forgot (apologies)
2024-01-09 08:57:41 -06:00
James E. Stine
f91b749f91
Fix typo missed with === on Issue #541
2024-01-08 22:01:52 -06:00
James E. Stine
79d7bb60ea
Address Issue #541 where CVTINT or CMP in testfloat were not checked. The solution was to check inside the nested for loop. This was done to avoid issue related to the values changing between each cvtint or subsequent operation
2024-01-08 21:28:47 -06:00
David Harris
d93684be21
Verilate running (slowly)
2024-01-07 21:30:33 -08:00
David Harris
7cd02351d9
Updated testbench to count size of signature without searching for x. Now runs with Verilator.
2024-01-07 09:00:19 -08:00
David Harris
caedab679a
Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
2024-01-07 07:14:12 -08:00
David Harris
34f97201ee
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-06 08:19:56 -08:00
David Harris
167e061a1c
Fixed truncated begin_signature in testbench
2024-01-06 08:19:46 -08:00
Rose Thompson
ab07d64195
Fixes coremark. Maybe works with verilator.
2024-01-06 00:41:57 -06:00
David Harris
ed623f1a71
Fixed unsupported riscof YAML string; preparing for Verilator -G testcase
2024-01-05 20:06:21 -08:00
David Harris
d229dc06ee
Coverage improvements; remove incorrect logic checking NAPOT nonleaf PTE
2024-01-02 00:35:17 -08:00
David Harris
52b6d1d163
restored tlbNAPOT coverage tests
2023-12-31 09:55:58 -08:00
David Harris
b3ff1035c4
Propagated MIP-based tracer interrupts to testbench-linux-imperas
2023-12-21 11:47:49 -08:00
David Harris
45b5658d06
Updated Imperas testbench to use MIP bits to communicate pending interrupts
2023-12-21 11:05:26 -08:00
David Harris
8552369687
Merged PR538, delete unused tests
2023-12-20 13:30:31 -08:00
Rose Thompson
70d0169019
All regression tests which matter are running!
2023-12-20 14:57:52 -06:00
Rose Thompson
1b59182d59
Updated tests with ending label.
2023-12-20 14:55:37 -06:00
Rose Thompson
b68dd74f89
Reverted logic to bit change.
2023-12-20 13:16:32 -06:00
Rose Thompson
a8ab3c8342
Ok that is a stange bug.
...
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
Rose Thompson
9ee1ffe8fe
Almost working with modelsim and verilator.
2023-12-20 11:29:31 -06:00
David Harris
5dbca251d8
Defined new Zicboz and Zcb tests
2023-12-19 13:24:11 -08:00
Rose Thompson
4f59bd492d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-19 12:06:04 -06:00
Rose Thompson
2e792606dd
More progress. Most tests are passing in modelsim.
2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3
Progress.
2023-12-18 20:23:19 -06:00
David Harris
6186181d46
Merge pull request #537 from ross144/main
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Almost having working Verilator. One issue in the testbench remains.
2023-12-18 18:13:56 -08:00
Rose Thompson
1e1759c258
Restored the one hack change which prevents verilator from working.
2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b
Yay! I got verilator to compile our testbench! Does it actually work I don't know.
2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04
Cleanup.
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Verilator still has issues with riscassertions.sv and the testbench
2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f
functionName.sv is now linting for rv64gc.
2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f
Closer to verilator support.
2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b
Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module.
2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8
More progress towards verilator.
2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
...
Progress towards verilator support.
2023-12-18 12:50:49 -06:00
David Harris
6ba3ae662f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-17 19:04:50 -08:00
James E. Stine
f4c1713ed4
Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes.
2023-12-17 20:55:06 -06:00
David Harris
6cb4a9e905
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-12-15 19:27:10 -08:00
David Harris
a138ef37b1
Switched to using riscv-arch-test rv32e_m suite. Need to rename it from rv32e_unratified (PR pending)
2023-12-15 19:26:50 -08:00
James E. Stine
8d8bad61d4
Fix to take care of Issue #507 . Issue was caused with time delay in testbench-fp.sv that interfered with the if statement in the DIVSQRT condition for generating a vector. This original time delay was given to guarantee that the previous operation would complete. However, the testbench was modified to make sure this would not happen and this time delay is not needed obviating any issue that caused Issue #507 . Some other small enhancements were made to the testbench-fp.sv for beautification, as well. A full test was run on the testbench to check its validity.
2023-12-15 17:02:11 -06:00
David Harris
38f4d9baf8
Use riscv-arch-test arch32e instead of outdated wally-riscv-arch-test wally32e
2023-12-15 05:05:53 -08:00
David Harris
68d96a929c
Fixed hierarchical path to EcallFaultM in testbench
2023-12-13 16:37:54 -08:00
David Harris
ff26baf7e8
Rolled back attempt to support Verilator
2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
David Harris
b268a3b9d3
Added SPI support to Imperas testbenches
2023-12-07 09:44:31 -08:00
David Harris
c0801263f1
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-23 20:43:22 -08:00
David Harris
bcc20c6bd5
Merge pull request #505 from stineje/main
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Update fix for cvtint testbench-fp
2023-11-23 20:43:00 -08:00
David Harris
3df4c13daa
Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support
2023-11-23 20:36:45 -08:00
David Harris
1f57df7f8b
Fixed reference to deleted atomic signal in cache
2023-11-23 20:29:10 -08:00
James E. Stine
1ab7522064
Update fix for cvtint testbench-fp
2023-11-23 17:56:51 -06:00
Rose Thompson
1dac4d221e
Disable the trace for normal operation.
2023-11-21 13:49:07 -06:00
Rose Thompson
c77a47b403
Output the instruction trace to the logs directory.
2023-11-21 13:47:58 -06:00
Rose Thompson
b02bd6c835
Finally we got the wally tracer working with linux.
2023-11-21 13:45:55 -06:00
Rose Thompson
3fd6d3464c
We are logging now.
2023-11-21 13:02:34 -06:00
Rose Thompson
6ff8d19157
Added code to the wallyTracer to support outputing an instruction trace.
2023-11-21 12:28:19 -06:00
Jacob Pease
a1e7158bd9
Merge branch 'main' of github.com:openhwgroup/cvw
2023-11-18 19:20:48 -06:00
David Harris
8baa5b2e7b
Merge pull request #483 from ross144/main
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Fixed branch predictor embench generation results
2023-11-17 10:07:30 -08:00
Rose Thompson
38b327eaf8
Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.
2023-11-17 11:21:25 -06:00
Jacob Pease
23e5fca2a7
Merge branch 'main' of github.com:jacobpease/cvw
2023-11-16 14:04:11 -06:00
David Harris
94201e993f
Merge pull request #481 from ross144/main
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Fixed the BTB logger so sim_bp correctly reports BTB performance
2023-11-15 17:45:38 -08:00
Rose Thompson
bc935b1b3b
Fixed second bug in the logger script when branch logging enabled but counter logger not.
2023-11-15 14:56:02 -06:00
Rose Thompson
5d4a89b27c
Fixed bug in the btb branch logging.
...
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
2023-11-15 14:51:47 -06:00
David Harris
cfaeeae25a
Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter
2023-11-15 08:15:01 -08:00
Rose Thompson
feb45b9b59
Patched up linux imperas testbench.
2023-11-14 14:20:13 -06:00
Rose Thompson
efc1d732d8
Fixed the imperas testbench to be compatible with the config changes.
2023-11-14 12:57:44 -06:00
David Harris
a77bea9954
Merge pull request #472 from ross144/main
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Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building
2023-11-14 08:34:06 -08:00
Rose Thompson
95fc5f4a1c
Towards removing the FPGA config file.
2023-11-13 17:20:26 -06:00
Rose Thompson
da59cb71a9
Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
2023-11-13 14:12:27 -06:00
Rose Thompson
540d8d930d
Cleanup.
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Linux makefile
wally tracer. probably reduce some complexity here.
2023-11-13 14:04:43 -06:00
David Harris
6ac83c776e
Cleaned up number of bits in fdivsqrt
2023-11-11 15:50:06 -08:00
David Harris
2bf5143163
Bug fixes related to size of fpdivsqrt bit count and number of cycles
2023-11-11 05:58:53 -08:00
David Harris
448ced00c5
Fixed testbench-fp to reflect signal name changes
2023-11-11 04:05:34 -08:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
Rose Thompson
baacb6f6eb
Missed tests.vh.
2023-11-10 16:10:10 -06:00
David Harris
bddd2d573e
Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
2023-11-05 07:06:53 -08:00
David Harris
b0dbf3a984
Testbench fixes to add SPI and make string pp static in testbench.fp to solve compiler issue
2023-11-04 20:36:05 -07:00
David Harris
568aa3c4a6
Verilator improvements
2023-11-04 03:21:07 -07:00
David Harris
4de21c206f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-03 16:04:10 -07:00
