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1165 Commits

Author SHA1 Message Date
bbracker
2c9c9328a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
Ross Thompson
f7583d0e0d Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
14e6d2c576 Converted flops to synchronous reset now that reset signal is synchronized 2021-10-25 11:49:20 -07:00
David Harris
47124f36c8 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
Ross Thompson
ebef47b1c9 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
eb9740bc31 manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
Ross Thompson
87aaec3b6c Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
dcd4d9dd9f add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
David Harris
106982e493 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34 more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
bb4ad264ce IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
b6bb33ecef lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
5e961973cb IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
708b914a65 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
817795f619 Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
2abec36221 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
6ae9aa7d80 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2 FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
5235e61d9e Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
bf3eb7b814 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
ff409d4fe7 Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
James E. Stine
a60e19dc3f Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Ross Thompson
f4e64c2eaf Added debug signals to dcache. 2021-10-20 15:52:05 -05:00
David Harris
687703f0d8 removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
James E. Stine
7536e0a2ee Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. 2021-10-20 12:00:41 -05:00
James E. Stine
ed179b0bd9 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
b65a4bd040 Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
Ross Thompson
77a89c30de Fixed bug with the external memory region selection. 
Updated bios program to copy just 127MB to dram.
 2021-10-19 11:23:23 -05:00
David Harris
8d08ca6a1e Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
df0b65e483 replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
David Harris
d0b9ebd2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
47f7a5db9c Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
d8d414665c fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
James E. Stine
d895fd7ee5 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
aafa988ca2 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
5a1835622c Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
33e5a078bf cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
6b30adb309 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Skylar Litz
395e070917 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
d639222519 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
eb64a7f0c9 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
Katherine Parry
09f51871c5 lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
4ea56ac68b some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
Ross Thompson
5fdac9fa3b Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Ross Thompson
c90d129498 Fixed boot loader program to start at correct address. 
modified script which converts the ram.txt into preload text file for sdc simulation.
created script to convert ram.txt into binary to write to flash card.
added top level for solo sd card fpga.
 2021-10-11 17:22:23 -05:00
Shreya Sanghai
51185478df made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
295a3c7af2 actually added redundant mul 2021-10-11 11:29:13 -07:00
Shreya Sanghai
324230e2f9 added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
fc39f77cba Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
Ross Thompson
cbf4e76d1c Fixed sdc byte and nibble orders. 2021-10-11 12:15:52 -05:00
Ross Thompson
3d9d4cc03f Partially working sd card reader. 2021-10-11 10:23:45 -05:00
David Harris
8a64675b02 intdiv cleanup 2021-10-11 08:14:21 -07:00
David Harris
a8ce4568aa Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
a077735ecc Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
David Harris
266c706804 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
77f1ae54d8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
8eff03bf1a simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
93e6ec96a7 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6d2d93deeb Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
2d09994a91 Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
644af40855 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
e93014d6d8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
e8d013b106 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
David Harris
99fd79c20b Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
44b023ace1 FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
kipmacsaigoren
086e6d130a rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
kipmacsaigoren
8e35701103 Merging new changes into the old one's I've made in the OKstate servers 2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
3623dfa51e removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions. 2021-10-08 15:33:18 -07:00
kipmacsaigoren
3103b78493 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-08 12:01:44 -05:00
bbracker
25e0745a6a fix div restarting bug 2021-10-07 18:55:00 -04:00
kipmacsaigoren
086a0234ba Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-06 11:52:34 -05:00
James E. Stine
b90d7b8083 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
kipmacsaigoren
4a9dd49785 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-04 12:28:03 -05:00
Ross Thompson
c10261f0ad Added more debug flags. 2021-10-03 11:41:21 -05:00
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
Ross Thompson
ec4a07de64 Movied tristate to test bench level. 2021-09-30 11:27:42 -05:00
Ross Thompson
db18aac9af Partially sd card read on fpga. 2021-09-30 11:23:09 -05:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
Ross Thompson
99070127d8 Added debugging directives to system verilog. 2021-09-27 13:57:46 -05:00
Ross Thompson
f2c1ca4bd5 added support to due partial fpga simulation. 2021-09-26 15:00:00 -05:00
Ross Thompson
6dc25e07c2 Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 
the flash card to dram.
Fixed latch issue in the sd card reader.
 2021-09-26 13:22:23 -05:00
Ross Thompson
55f3c15302 Merge branch 'sdc' into fpga 2021-09-25 19:33:07 -05:00
Ross Thompson
3a15cc7872 We now have a rough sdc read routine. 2021-09-25 17:51:38 -05:00
Ross Thompson
dd9fe60b28 Write of the SDC address register is correct. The command register is not yet working. 
The root problem is the command register needs to be reset at the end of the SDC transaction.
 2021-09-24 18:48:11 -05:00
Ross Thompson
5663522a3f Now have software interacting with the initialization and settting the address register. 2021-09-24 18:30:26 -05:00
Ross Thompson
232d4a554f Have program which checks for sdc init and issues read, but read done is 
not correctly being read back by the software.  The error is in how the
sdc indicates busy.
 2021-09-24 15:53:38 -05:00
Ross Thompson
71e20c7f61 Fixed lint errors in the SDC. 2021-09-24 12:38:48 -05:00
Ross Thompson
af28cfb70c Added SDC defines to each config mode. 
Added sd_top which is the sd card reader.
 2021-09-24 12:24:30 -05:00
Ross Thompson
0a33f5fa46 setup so the sdc does not need to load a model in the imperas test bench. 2021-09-24 11:30:52 -05:00
Ross Thompson
78028947bf Updated Imperas test bench to work with the SDC reader. 2021-09-24 11:22:54 -05:00
Ross Thompson
4256ef82b1 SDC to ABHLite interface partially done. 
Added SDC to adrdec and uncore.
 2021-09-24 10:45:09 -05:00
Ross Thompson
a182263b1c Added clock gater and divider to generate the SDCCLK. 2021-09-23 17:58:50 -05:00
Ross Thompson
9ed7a1f494 Partial implementation of SDC AHBLite interface. 2021-09-23 17:45:45 -05:00
Ross Thompson
0f7be5e591 Started the AHBLite to SDC interface. 2021-09-22 18:08:38 -05:00
Ross Thompson
d4f514010d Changes to make fpga synthesizable. 
Added preload to test simple program on wally in fpga.
 2021-09-22 10:54:13 -05:00
Ross Thompson
f5905f33d3 Initial SD Card reader. 2021-09-22 10:50:29 -05:00
kipmacsaigoren
afd73ddada Merge branch 'ppa' into main 2021-09-20 01:01:47 -05:00
Ross Thompson
d09b381183 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Kip Macsai-Goren
f1981a1267 more input changes on prioirty thermometer. passes lint 2021-09-17 13:07:21 -04:00
kipmacsaigoren
f48c780ec2 added new fun ways of putting inputs into the priority thermometer 2021-09-17 12:00:38 -05:00
Ross Thompson
8fa287a449 The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00