cvw/wally-pipelined/src
2021-10-02 09:38:02 -04:00
..
cache Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
ebu Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
fpu Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
generic Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
hazard The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
ieu Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
ifu Updated Dcache to fully support flush. This appears to work. 2021-09-17 10:25:21 -05:00
lsu Finished adding the d cache flush. Required ensuring the write data, address, and size are 2021-09-17 13:03:04 -05:00
mmu Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
muldiv Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
privileged Revert "first attempt at verilog side of checkpoint functionality" 2021-09-30 20:45:26 -04:00
uncore Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
wally Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00