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https://github.com/openhwgroup/cvw
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more lsu/ifu lint cleanup
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parent
8b1dc81d34
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wally-pipelined/src
5
wally-pipelined/src/cache/icache.sv
vendored
5
wally-pipelined/src/cache/icache.sv
vendored
@ -77,10 +77,9 @@ module icache
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logic FlushMem;
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logic ICacheMemWriteEnable;
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logic [BLOCKLEN-1:0] ICacheMemWriteData;
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logic [`PA_BITS-1:0] PCTagF, PCNextIndexF;
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logic [`PA_BITS-1:0] PCTagF;
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// Output signals from cache memory
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logic [31:0] ICacheMemReadData;
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logic ICacheMemReadValid;
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logic ICacheReadEn;
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logic [BLOCKLEN-1:0] ReadLineF;
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@ -101,7 +100,6 @@ module icache
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logic CntReset;
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logic [1:0] SelAdr;
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logic SavePC;
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logic [INDEXLEN-1:0] RAdr;
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logic [NUMWAYS-1:0] VictimWay;
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logic LRUWriteEn;
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@ -302,7 +300,6 @@ module icache
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.CntEn,
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.CntReset,
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.SelAdr,
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.SavePC,
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.LRUWriteEn
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);
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2
wally-pipelined/src/cache/icachefsm.sv
vendored
2
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -61,7 +61,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
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output logic CntEn,
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output logic CntReset,
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output logic [1:0] SelAdr,
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output logic SavePC,
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output logic LRUWriteEn
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);
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@ -117,6 +116,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
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statetype CurrState, NextState;
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logic PreCntEn;
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logic UnalignedSelect;
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logic SavePC; // unused right now *** consider deleting
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// the FSM is always runing, do not stall.
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always_ff @(posedge clk, posedge reset)
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@ -87,7 +87,7 @@ module ifu (
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logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
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logic PrivilegedChangePCM;
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logic IllegalCompInstrD;
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logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD;
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logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
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logic [`XLEN-3:0] PCPlusUpperF;
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logic CompressedF;
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logic [31:0] InstrRawD, FinalInstrRawF;
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@ -45,7 +45,6 @@ module lsu
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input logic FlushDCacheM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic DataMisalignedM,
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output logic DCacheMiss,
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output logic DCacheAccess,
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@ -94,6 +93,7 @@ module lsu
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);
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logic DTLBPageFaultM;
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logic DataMisalignedM;
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logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache
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@ -80,7 +80,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
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);
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logic [`PA_BITS-1:0] TLBPAdr;
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logic PMPSquashBusAccess, PMASquashBusAccess;
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// Translation lookaside buffer
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logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;
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@ -32,12 +32,8 @@ module pmachecker (
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [1:0] Size,
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
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output logic Cacheable, Idempotent, AtomicAllowed,
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output logic PMASquashBusAccess,
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output logic PMAInstrAccessFaultF,
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output logic PMALoadAccessFaultM,
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output logic PMAStoreAccessFaultM
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@ -65,6 +61,5 @@ module pmachecker (
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assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
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assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault;
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assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault;
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assign PMASquashBusAccess = PMAAccessFault;
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endmodule
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@ -41,11 +41,7 @@ module pmpchecker (
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// which we might not intend.
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
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output logic PMPSquashBusAccess,
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output logic PMPInstrAccessFaultF,
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output logic PMPLoadAccessFaultM,
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output logic PMPStoreAccessFaultM
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@ -79,6 +75,6 @@ module pmpchecker (
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assign PMPStoreAccessFaultM = EnforcePMP && WriteAccessM && ~|W;
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assign PMPLoadAccessFaultM = EnforcePMP && ReadAccessM && ~|R;
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assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
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//assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
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endmodule
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