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more lsu/ifu lint cleanup

This commit is contained in:
David Harris 2021-10-23 12:10:13 -07:00
parent 8b1dc81d34
commit 106982e493
7 changed files with 5 additions and 18 deletions

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@ -77,10 +77,9 @@ module icache
logic FlushMem;
logic ICacheMemWriteEnable;
logic [BLOCKLEN-1:0] ICacheMemWriteData;
logic [`PA_BITS-1:0] PCTagF, PCNextIndexF;
logic [`PA_BITS-1:0] PCTagF;
// Output signals from cache memory
logic [31:0] ICacheMemReadData;
logic ICacheMemReadValid;
logic ICacheReadEn;
logic [BLOCKLEN-1:0] ReadLineF;
@ -101,7 +100,6 @@ module icache
logic CntReset;
logic [1:0] SelAdr;
logic SavePC;
logic [INDEXLEN-1:0] RAdr;
logic [NUMWAYS-1:0] VictimWay;
logic LRUWriteEn;
@ -302,7 +300,6 @@ module icache
.CntEn,
.CntReset,
.SelAdr,
.SavePC,
.LRUWriteEn
);

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@ -61,7 +61,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
output logic CntEn,
output logic CntReset,
output logic [1:0] SelAdr,
output logic SavePC,
output logic LRUWriteEn
);
@ -117,6 +116,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
statetype CurrState, NextState;
logic PreCntEn;
logic UnalignedSelect;
logic SavePC; // unused right now *** consider deleting
// the FSM is always runing, do not stall.
always_ff @(posedge clk, posedge reset)

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@ -87,7 +87,7 @@ module ifu (
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic PrivilegedChangePCM;
logic IllegalCompInstrD;
logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD;
logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
logic [`XLEN-3:0] PCPlusUpperF;
logic CompressedF;
logic [31:0] InstrRawD, FinalInstrRawF;

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@ -45,7 +45,6 @@ module lsu
input logic FlushDCacheM,
output logic CommittedM,
output logic SquashSCW,
output logic DataMisalignedM,
output logic DCacheMiss,
output logic DCacheAccess,
@ -94,6 +93,7 @@ module lsu
);
logic DTLBPageFaultM;
logic DataMisalignedM;
logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache

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@ -80,7 +80,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
);
logic [`PA_BITS-1:0] TLBPAdr;
logic PMPSquashBusAccess, PMASquashBusAccess;
// Translation lookaside buffer
logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;

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@ -32,12 +32,8 @@ module pmachecker (
input logic [`PA_BITS-1:0] PhysicalAddress,
input logic [1:0] Size,
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
output logic Cacheable, Idempotent, AtomicAllowed,
output logic PMASquashBusAccess,
output logic PMAInstrAccessFaultF,
output logic PMALoadAccessFaultM,
output logic PMAStoreAccessFaultM
@ -65,6 +61,5 @@ module pmachecker (
assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault;
assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault;
assign PMASquashBusAccess = PMAAccessFault;
endmodule

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@ -41,11 +41,7 @@ module pmpchecker (
// which we might not intend.
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
output logic PMPSquashBusAccess,
output logic PMPInstrAccessFaultF,
output logic PMPLoadAccessFaultM,
output logic PMPStoreAccessFaultM
@ -79,6 +75,6 @@ module pmpchecker (
assign PMPStoreAccessFaultM = EnforcePMP && WriteAccessM && ~|W;
assign PMPLoadAccessFaultM = EnforcePMP && ReadAccessM && ~|R;
assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
//assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
endmodule