cvw/wally-pipelined/src
Ross Thompson 6dc25e07c2 Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies
the flash card to dram.
Fixed latch issue in the sd card reader.
2021-09-26 13:22:23 -05:00
..
cache Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
ebu Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
fpu Changes to make fpga synthesizable. 2021-09-22 10:54:13 -05:00
generic Changes to make fpga synthesizable. 2021-09-22 10:54:13 -05:00
hazard The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
ieu Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
ifu Updated Dcache to fully support flush. This appears to work. 2021-09-17 10:25:21 -05:00
lsu Finished adding the d cache flush. Required ensuring the write data, address, and size are 2021-09-17 13:03:04 -05:00
mmu Have program which checks for sdc init and issues read, but read done is 2021-09-24 15:53:38 -05:00
muldiv Restored old integer divider 2021-09-12 22:07:52 -04:00
privileged Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
sdc Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 2021-09-26 13:22:23 -05:00
uncore Merge branch 'sdc' into fpga 2021-09-25 19:33:07 -05:00
wally Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies 2021-09-26 13:22:23 -05:00