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Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.
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wally-pipelined/src/cache/sram1rw.sv
vendored
8
wally-pipelined/src/cache/sram1rw.sv
vendored
@ -14,13 +14,19 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
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);
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logic [WIDTH-1:0][DEPTH-1:0] StoredData;
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logic [$clog2(WIDTH)-1:0] AddrD;
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always_ff @(posedge clk) begin
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ReadData <= StoredData[Addr];
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AddrD <= Addr;
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if (WriteEnable) begin
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StoredData[Addr] <= #1 WriteData;
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end
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end
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assign ReadData = StoredData[AddrD];
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endmodule
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/* verilator lint_on ASSIGNDLY */
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