Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.

This commit is contained in:
Ross Thompson 2021-10-24 21:21:49 -05:00
parent 87aaec3b6c
commit ebef47b1c9

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@ -14,13 +14,19 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
);
logic [WIDTH-1:0][DEPTH-1:0] StoredData;
logic [$clog2(WIDTH)-1:0] AddrD;
always_ff @(posedge clk) begin
ReadData <= StoredData[Addr];
AddrD <= Addr;
if (WriteEnable) begin
StoredData[Addr] <= #1 WriteData;
end
end
assign ReadData = StoredData[AddrD];
endmodule
/* verilator lint_on ASSIGNDLY */