David Harris 3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.		2021-10-23 06:15:26 -07:00
..
cache	replaced flopenl with flopenr when clearing to 0	2021-10-18 16:53:18 -07:00
ebu	Additional cleanup of ahblite.	2021-08-25 22:53:20 -05:00
fpu	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
generic	Changed some flops to settable	2021-10-18 17:05:29 -07:00
hazard	The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.	2021-09-17 10:33:57 -05:00
ieu	Added more pipeline stage suffixes to divider	2021-10-02 22:54:01 -04:00
ifu	simplify flopenrc's that didn't actually need to be flopenrc's	2021-10-10 12:25:05 -07:00
lsu	Finished adding the d cache flush. Required ensuring the write data, address, and size are	2021-09-17 13:03:04 -05:00
mmu	fixed issues with dc shell not liking modules with parameters without default values.	2021-10-18 17:24:15 -05:00
muldiv	Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this	2021-10-19 12:09:43 -05:00
privileged	Changed some flops to settable	2021-10-18 17:05:29 -07:00
uncore	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
wally	removed .* from wallypipeliendsoc	2021-10-20 13:49:18 -07:00