IEU lint cleanup

wally-pipelined/src/ieu/controller.sv

@@ -34,9 +34,8 @@ module controller(
   output logic [2:0] ImmSrcD,
   input  logic       IllegalIEUInstrFaultD, 
   output logic       IllegalBaseInstrFaultD,
-  output logic       RegWriteD,
   // Execute stage control signals
-  input logic 	     StallE, FlushE, 
+  input logic 	     StallE, FlushE,  
   input logic  [2:0] FlagsE, 
   output logic       PCSrcE,        // for datapath and Hazard Unit
   output logic [4:0] ALUControlE, 
@@ -46,7 +45,6 @@ module controller(
   output logic [2:0] Funct3E,
   output logic       MulDivE, W64E,
   output logic       JumpE,	
-  output logic [1:0] MemRWE,	  
   // Memory stage control signals
   input  logic       StallM, FlushM,
   output logic [1:0] MemRWM,
@@ -57,7 +55,7 @@ module controller(
   output logic [2:0] Funct3M,
   output logic       RegWriteM,     // for Hazard Unit
   output logic       InvalidateICacheM, FlushDCacheM,
-  output logic       InstrValidM, InstrValidW,
+  output logic       InstrValidM, 
   // Writeback stage control signals
   input  logic       StallW, FlushW,
   output logic 	     RegWriteW,     // for datapath and Hazard Unit
@@ -75,9 +73,9 @@ module controller(
   `define CTRLW 24
 
   // pipelined control signals
-  logic 	    RegWriteE;
+  logic 	    RegWriteD, RegWriteE;
   logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM;
-  logic [1:0] MemRWD;
+  logic [1:0] MemRWD, MemRWE;
   logic		    JumpD;
   logic		    BranchD, BranchE;
   logic	[1:0] ALUOpD;
@@ -233,8 +231,8 @@ module controller(
   
   // Writeback stage pipeline control register
   flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
-                         {RegWriteM, ResultSrcM, InstrValidM},
-                         {RegWriteW, ResultSrcW, InstrValidW});  
+                         {RegWriteM, ResultSrcM},
+                         {RegWriteW, ResultSrcW});  
 
   assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;
 

wally-pipelined/src/ieu/ieu.sv

@@ -85,8 +85,6 @@ module ieu (
   logic        TargetSrcE;
   logic        SCE;
   logic        InstrValidW;
-  logic [1:0]  MemRWE;
-  logic        RegWriteD;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E;

wally-pipelined/src/uncore/uncore.sv

@@ -47,9 +47,6 @@ module uncore (
   input  logic [2:0]       HADDRD,
   input  logic [3:0]       HSIZED,
   input  logic             HWRITED,
-  // bus interface
-  // PMA checker now handles access faults. *** This can be deleted
-  // output logic             DataAccessFaultM,
   // peripheral pins
   output logic             TimerIntM, SwIntM, ExtIntM,
   input  logic [31:0]      GPIOPinsIn,
@@ -63,14 +60,13 @@ module uncore (
   logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART;
 
   logic [6:0]      HSELRegions;
-  logic            HSELTim, HSELCLINT, HSELPLIC, HSELGPIO, PreHSELUART, HSELUART;
+  logic            HSELTim, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART;
   logic            HSELTimD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD;
   logic            HRESPTim, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART;
   logic            HREADYTim, HREADYCLINT, HREADYPLIC, HREADYGPIO, HREADYUART;  
   logic [`XLEN-1:0] HREADBootTim; 
   logic            HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim;
   logic            HSELNoneD;
-  logic [1:0]      MemRWboottim;
   logic            UARTIntr,GPIOIntr;
 
   // Determine which region of physical memory (if any) is being accessed

wally-pipelined/src/wally/wallypipelinedsoc.sv

@@ -54,32 +54,25 @@ module wallypipelinedsoc (
   output logic             UARTSout
 );
 
-  // to instruction memory *** remove later
-  logic [`XLEN-1:0] PCF;
-
   // Uncore signals
   logic [`AHBW-1:0] HRDATA;   // from AHB mux in uncore
   logic             HREADY, HRESP;
-  logic             InstrAccessFaultF, DataAccessFaultM;
   logic             TimerIntM, SwIntM; // from CLINT
   logic [63:0]      MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs
   logic             ExtIntM; // from PLIC
   logic [2:0]       HADDRD;
   logic [3:0]       HSIZED;
   logic             HWRITED;
-  logic [31:0]      InstrF;
    
   // instantiate processor and memories
   wallypipelinedhart hart(.clk, .reset,
-    .PCF,  .TimerIntM, .ExtIntM, .SwIntM, .DataAccessFaultM, 
+    .TimerIntM, .ExtIntM, .SwIntM, 
     .MTIME_CLINT, .MTIMECMP_CLINT, 
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
     .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
     .HADDRD, .HSIZED, .HWRITED
    );
 
-  // instructions now come from uncore memory. This line can be removed at any time.
-  // imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
   uncore uncore(.HCLK, .HRESETn,
     .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
     .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,